Via Management

Managing Vias in Very High Data-Rate Differential Pairs

Managing via structures can minimize signal degradation and enable differential pairs to operate at data rates as high as 56Gb/s.
by Lee Ritchey

Vias are the plated through-holes in a printed circuit board used to connect device signal pins to the traces in the PCB. As shown in Figure 1, for signals whose frequency content is below three gigahertz, the effects of these vias are visible but not significant. The dip in the signal is caused by the via’s parasitic capacitance. (This plot was used to show that a right-angle bend does not cause a signal integrity problem.)

Figure 1. Reflection from the via used to access a signal net below 3 gigahertz.

For signals with useful frequencies above three gigahertz, the foregoing may not be true. In fact, not knowing about these via effects and doing something to minimize them can result in signal degradation so severe that the data path does not function. This article explains why this happens and how to minimize these effects. For data rates as high as 56Gb/s, it’s necessary to use low-loss laminates.

Figure 2 is a loss vs. frequency plot of two eight-inch-long traces routed in two different signal layers on the same 16-layer PCB. As shown, up to about 3GHz, the loss vs. frequency is about the same for both traces. Above 3GHz, the trace represented by the blue curve develops a very large amount of loss (44dB at 8GHz) and, if something isn’t done to minimize the effect of the vias on this trace, it will not operate correctly.

Figure 2. Loss versus frequency for two eight-inch traces on different signal layers.

Next, as shown, when the signal travels the length of the via, as the red trace does, the via’s effect on the loss curve is minimized. This is one solution to the problem. However, it only works when these traces can be routed on the signal layers near the bottom of the PCB.

Figure 3 is loss vs. frequency for three traces, all routed on the same signal layer. The red and green traces have only a via at each end to connect to signal pins. The vias on the red trace have the unwanted part of the via extending below the trace layer drilled away using a technique called backdrilling. This method adds additional cost to PCB fabrication. Plus, it requires careful monitoring so the PCB is not made unusable as a result of backdrilling. The blue trace has an additional via along its length, which might be used to change signal layers. It has not been backdrilled.

Figure 3. Loss versus frequency for three traces routed on the same signal layer.

This article illustrates two methods for minimizing the effect of vias on transmission lines. There are a total of four methods that can be used. They include:

  1. Routing the signals on layer one and using no vias.
  2. Routing the signals on layer two and using blind vias to access the trace. Figure 4 illustrates this method.
  3. Routing the signals on layers near the bottom of the PCB.
  4. Routing the signals on layers not near the bottom of the PCB and backdrilling away the unwanted portion of the via.
Figure 4. Routing signals on layer two and accessing the trace with blind vias.

All four routing methods described above have disadvantages. Methods one, two and three only work when the number of signals to be routed will fit in the space available on their respective layers. Method four carries with it the added cost of backdrilling and the risk that a drill may penetrate too deep and sever the connection between the via and the signal trace.

Routing only on layer one has the disadvantage that the outer layers have the poorest impedance control of all the signal layers in a PCB.

Figure 5 is an illustration of backdrilling. Some designs, such as backplanes, may require several different drill depths depending on which layer signals are routed.

Figure 5. Backdrilling removes the unused portion of a via below the signal layer.

With careful management of the vias used to connect signal pins to each other, it is possible to achieve data rates as high as 56Gb/s in PCBs.End of article content

Lee Ritchey is president of Speeding Edge (speedingedge.com); lritchey49@aol.com.