De-Embedding DC: Removing Resistance Effects in Impedance Measurements

Measuring characteristic impedance on PCBs with line widths over 75 microns is fairly simple. But below 20 microns, things begin to get a little dicey.

In PCBs with traces of 75 microns or above, measuring characteristic impedance is a straightforward affair. But as dimensions drop to 20 microns or less, PCB fabricators and designers must de-embed the effect of DC resistance, which shows up as a rising reflection from the TDR measurement.

Solver and impedance measurements do correlate. Characteristic impedance is an inherent property of a transmission line, and it does not vary with length. When traces measure 75 microns and above, time-domain reflectometers (TDR) and vector network analyzers (VNA) operating in the time domain return a flat reflection over the length of the tested line, as shown in Figure 1.

So, what changes at 20 microns? At line widths above 50 to 75 microns, the DC resistance of a PCB transmission line is small compared with the characteristic. But as line width reduces, the resistance appears to “pile up” on the TDR reflection. This is not the characteristic impedance changing: If you cut the line at any point and measure with a TDR, it will always start at the characteristic impedance. The only problem is that the reflection is disturbed by interconnect aberrations at the launch. Figure 2 illustrates a trace with a sub-50-micron line width, and it illustrates the rise on the reflected trace:

What not to do. If you are unaware of the “why,” and this has happened from time to time when fabricators take a chance on it, some imaginative people suspect the Dk is incorrect and use a field solver to “goal seek the Dk.” This is an incorrect approach. The correct approach is to remove the effect of the DC resistance component on the reflection. So, how to achieve that?

Launch point extrapolation. Because the DC resistance superimposes a steady rise on the trace, it is possible to fit a regression line on the TDR trace and project back to the physical start of the trace. (Recall the earlier example – on the TDR trace, the actual point is masked by launch aberration.) Applying launch point extrapolation (LPE) simply draws a line back to the hidden point at the start of the trace. This gives us the characteristic impedance. Note that we are not ignoring the DC resistance – this is a characteristic of the line. But it is not the characteristic impedance. Figure 3 shows the line from Figure 2 with LPE regression used to de-embed DC resistance.

Measuring at the Lower Limits of Subtractive Manufacture

Figure 4 illustrates the measurement of a differential pair at the lower limits of subtractive fabrication.

At these dimensions, the DC resistance of the trace is significant, and using a raw reflection from TDR or VNA with the time-domain option will lead to the impression that the measured and modeled impedances do not correlate. The simple action of removing the DC resistance component from the reflection will lead to the correct correlation.

Figure 5 depicts an easy way to predict the impact of DC resistance on TDR traces.

By feeding the copper geometry and resistivity into the Polar TRC Plus, you can predict whether you need to ask your fabricator to use LPE in order to achieve correlation between solver and measured results for controlled (characteristic) impedance.

When traces get below 20 microns, measuring characteristic impedance really starts to get interesting.End of article content

 

REFERENCES

1. James A. Strickland, Time Domain Reflectometry Measurements, published by Tektronix, 1970. An invaluable resource, now out of print but available online and occasionally in print used.
2. Polarinstruments.com application notes and youtube.com/@polarinc.

Martyn Gaudion is managing director of Polar Instruments.