Embedded Power

Embedded Die Substrate Technology

Embedded die substrate technology combines thick copper heat spreaders, sintered silver die attach and copper microvias to improve thermal management, reduce parasitic inductance and increase switching performance in wide-bandgap power electronics.
by Chris Parker

GaN and SiC transistors switch at high speeds, enabling smaller passive components, higher power density, and improved efficiency. However, the packages, interconnects, and PCB traces surrounding these devices introduce parasitic inductance into the power loop. Even small amounts of inductance can cause voltage overshoot and limit switching performance.

Studies of conventional wire-bonded power modules report loop inductances ranging from 6.7 to 15nH. Reducing loop inductance can decrease voltage overshoot, improving efficiency and reliability. As switching speeds continue to increase, package and layout design can become limiting factors rather than the transistors themselves.

Thermal management presents a similar challenge. Traditional power modules conduct heat through multiple layers, including die attach, substrate, baseplate, thermal interface material (TIM), and heat sink. Each layer adds thermal resistance, while FR-4 circuit boards further restrict heat flow because of their low thermal conductivity.

Embedded die packaging addresses these electrical and thermal limitations by placing the die inside the PCB structure and replacing wire bonds with short copper microvias. This approach can reduce inductance and improve heat transfer.

The embedded die substrate (EDS) architecture developed by TCLAD uses a thick copper heat spreader as its structural foundation rather than an organic laminate core. This construction shortens the thermal path and allows designers to integrate electrical interconnections using established PCB fabrication processes.

Existing Embedded Die Approaches

Several embedded die packaging approaches replace wire bonds with copper microvias and integrate semiconductor dies within PCB structures. The primary differences involve die support, electrical isolation, and heat removal.

For example, Infineon’s S-Cell and Schweizer Electronic’s p² Pack embed prepackaged SiC switching cells within multilayer PCB structures. Published results indicate parasitic inductance of approximately 1–1.5nH. However, heat must pass through a thermally conductive prepreg layer before reaching the cooling system. Reported thermal resistance for individual cells can be approximately 20% higher than that of comparable ceramic-substrate modules. Distributing multiple cells across a larger board can reduce thermal interaction between devices.

Other approaches, including AT&S’s embedded component packaging (ECP), use laser-machined cavities in laminate layers to accommodate embedded components. Fraunhofer IZM has also demonstrated embedded SiC devices using sintered die attach on insulated metal substrate (IMS) or direct bonded copper (DBC) structures, reporting low loop inductance and voltage overshoot of approximately 4% during switching.

In some embedded constructions, heat must pass through an organic material with thermal conductivity of approximately 3W/m·K before reaching a metal heat spreader.

The EDS architecture differs by placing a thick copper heat spreader directly beneath the die at the beginning of the stackup. Rather than relying on a laminate core for structural support, the copper layer serves as both the die carrier and the primary heat-spreading element. This changes the thermal path and reduces dependence on organic materials for heat transfer.

Table 1. Embedded Die Architectures for Power Electronics

Embedded Die Substrate Architecture

The EDS architecture begins with a thick copper layer, up to 1mm, that serves as both a structural element and a heat spreader. Instead of embedding a copper slug in a laminate substrate, this approach machines package features directly into the copper.

The process creates two types of cavities. A thermally conductive, electrically insulating dielectric fills the isolation regions, which the fabrication process then planarizes. Precision machining creates die pockets at controlled depths to establish the required die height.

Low-pressure silver sintering attaches each die inside its pocket. Sintered silver provides thermal conductivity of 150W/m·K or greater, compared with approximately 58W/m·K for SAC305 solder.

The process forms the sintered joint at approximately 250°C. Because silver has a melting point of 961°C, the joint does not remelt during conventional subsequent board processing.

Published reliability data indicate that sintered silver die attach can achieve power cycling lifetimes up to 10 times longer than solder attach, although actual performance depends on the materials, joint geometry, and operating conditions.

The recessed die placement also supports the flat surface required for subsequent lamination. After die attach, the process laminates copper foil over the embedded devices under controlled temperature and pressure. Laser drilling and copper plating create microvias that connect directly to the gate, source, and drain pads.

These plated connections replace conventional wire bonds.

Designers can then add additional routing layers sequentially, allowing them to place gate-drive and control circuitry above the embedded power stage.

The evaluated construction uses SPL-15, an electrically insulating dielectric with thermal conductivity of 10W/m·K, between copper layers. This is higher than the approximately 3W/m·K conductivity reported for some embedded leadframe insulation materials.

Higher dielectric thermal conductivity can support greater insulation thickness while limiting the corresponding increase in thermal resistance. Designers must still account for dielectric breakdown strength, operating voltage, material thickness, and applicable safety requirements.

Architecture Development and Stackup Considerations

Two earlier prototype constructions informed the evaluated architecture.

The first placed a semiconductor die on a 3mm copper slug embedded in thick FR-4. Differences in the coefficient of thermal expansion (CTE) among the copper, FR-4, and build-up materials produced stresses that cracked the microvias.

The second construction replaced the copper slug with a balanced stackup consisting of two thick copper layers on opposite sides of an SPL-15 dielectric core. The symmetrical structure distributed thermal and mechanical stresses more evenly, maintained panel flatness, and eliminated the microvia cracking observed in the earlier prototype.

These results illustrate the importance of mechanical balance when combining embedded semiconductor devices, thick copper, dielectric materials, and plated interconnections. Material selection and stackup symmetry should be evaluated together rather than independently.

Figure 1. Comparison of the initial copper slug construction and revised balanced stackup, illustrating how symmetrical copper layers and a thermally conductive dielectric core reduce mechanical stress and prevent microvia cracking.

Half-Bridge Demonstrator

A half-bridge circuit served as the test vehicle for the EDS architecture. Half-bridge circuits are common building blocks for inverters and DC-DC converters.

The evaluation involved collaboration with a U.S. aerospace and defense manufacturer. The fabrication process placed bare GaN and SiC dies into precision-milled pockets and attached them using sintered silver. Plated copper microvias provided electrical connections to the embedded devices.

Two additional signal and drive layers were laminated above the power stage.

Figure 2 shows a cross section of the assembled test coupon. The demonstrator used standard FR-4 for the build-up layers because those layers carried only low-power control signals.

Applications requiring the build-up layers to carry additional heat or current may use higher-thermal-conductivity materials, including SPL-15 or SFL-series laminates, depending on the electrical and thermal requirements.

Figure 2. Cross-section of the embedded half-bridge coupon showing vertical microvia interconnections between the embedded dies and the upper circuit layers.

Electrical Performance

All evaluated samples passed functional testing at rated power. Voltage overshoot at the switching node remained below 2% of the supply voltage. The extracted power loop inductance ranged from 1 to 2nH.

The EDS demonstrator also achieved switching speeds approximately six times faster than an equivalent surface-mount design using the same semiconductor devices in standard packages.

Figure 3 illustrates the assembly configuration with two embedded dies.

Figure 3. Embedded semiconductor in SPL15-HT.

For comparison, published measurements of conventional wire-bonded modules report loop inductances ranging from 6.7 to 15nH. Other embedded leadframe and laminate constructions have demonstrated values of approximately 1–1.5nH.

These results place the evaluated EDS architecture within the range reported for other low-inductance embedded packaging approaches. Its principal structural distinction is the use of a continuous thick copper heat spreader as the die carrier rather than a prepackaged leadframe cell or laminate-supported die.

Thermal Path

Thermal performance depends on the number of interfaces along the heat flow path and the thermal resistance of each material.

Table 2 compares the junction-to-heat-sink thermal paths of several power electronics packaging architectures.

Table 2. Junction-to-Heat-Sink Thermal Path Comparison

Conventional wire-bonded power modules may include six or more material interfaces between the semiconductor junction and cooling surface. The evaluated EDS construction uses sintered silver die attach, a thick copper heat spreader, and a thermally conductive isolation dielectric to shorten the thermal path.

Sintered silver provides thermal conductivity of approximately 150W/m·K, compared with approximately 58W/m·K for SAC305 lead-free solder.

The SPL-15 isolation dielectric provides thermal conductivity of 10W/m·K, compared with approximately 3W/m·K for certain prepreg materials used in other embedded constructions.

For a heat transfer area of 1cm², a 100µm isolation layer contributes approximately 0.33K/W of thermal resistance at 3W/m·K. At 10W/m·K, the same thickness contributes approximately 0.10K/W.

These calculations illustrate the effect of dielectric thermal conductivity on the heat transfer path. The monolithic copper heat spreader, which can reach 1mm in thickness, also allows heat to spread laterally before reaching the isolation dielectric. Copper has a thermal conductivity of approximately 390W/m·K, making the spreader an important element of the thermal design.

In smaller embedded leadframe cells, the dimensions of the prepackaged cell limit the area available for lateral heat spreading. A continuous copper substrate can distribute heat across a larger area and allow multiple devices to share a common thermal path.

This distinction is particularly relevant when multiple power devices operate within the same substrate. Rather than relying on separate die carriers, the construction provides a shared copper heat-spreading plane.

The evaluated EDS architecture does not include a conventional baseplate-to-heat-sink TIM within the described substrate stack. However, the complete cooling assembly must still account for the thermal resistance of its final mechanical and thermal interfaces.

Reliability Considerations

Embedded die constructions combine semiconductor devices, copper layers, dielectric materials, and plated microvias into an integrated structure.

Temperature changes cause these materials to expand and contract. Differences in CTE can generate mechanical stresses at material interfaces and electrical interconnections.

The initial copper-slug prototype demonstrated this risk when thermal expansion differences contributed to microvia cracking. The revised construction uses SPL-15, which has a CTE of approximately 11.7ppm/°C below its glass transition temperature (Tg), providing a closer match to copper. The dielectric’s Tg of approximately 270°C also supports dimensional stability during lamination and reflow processing.

A mechanically balanced stackup, with comparable copper thicknesses on opposite sides of the dielectric core, helps distribute thermal stresses and maintain panel flatness. Sintered silver die attach introduces additional reliability considerations and potential benefits.

The process forms the joint at approximately 250°C, while silver has a melting point of 961°C. Published power cycling comparisons indicate that sintered silver joints can withstand up to 10 times as many cycles as certain solder-attached constructions.

Replacing wire bonds with plated copper microvias also removes the bond-heel fatigue mechanism associated with conventional wire-bonded assemblies.

However, embedded microvias introduce their own reliability requirements, including accurate registration, adequate plating, and resistance to thermomechanical fatigue. The evaluated process identified a via-to-die registration window of approximately 50µm.

Maintaining this registration tolerance is important for consistent electrical connections and manufacturing yield.

Applications and Further Development

Embedded die substrate architectures may support applications that require high power density, efficient heat removal, and fast switching speeds.

Potential applications include high-density DC-DC converters, motor drives, onboard chargers, transformer-integrated power stages, and power electronics for aerospace and defense systems.

These applications place significant demands on electrical interconnections, thermal management, insulation, and mechanical reliability.

The use of established PCB fabrication processes may allow manufacturers to integrate portions of the power semiconductor packaging process into circuit board fabrication.

In the EDS approach, the PCB fabricator can perform several operations traditionally associated with semiconductor packaging, including die integration, electrical interconnection, and substrate-level thermal management.

This could expand the PCB fabricator’s role from supplying interconnect structures to integrating portions of the wide-bandgap power stage itself.

However, implementation requires careful control of die placement, sintering, lamination, microvia formation, and material compatibility.

Further development should address via-to-die registration, dielectric material selection, thermal cycling reliability, and the transition from test coupons to full application-level power stages.

Additional comparative testing would also help establish performance differences among thick copper embedded die substrates, laminate-based embedded packages, and conventional power modules under equivalent operating conditions.

Key Takeaways

  • The EDS architecture places bare GaN and SiC semiconductor devices inside precision-milled pockets in a thick copper heat spreader, creating a shortened thermal path through the substrate.
  • Sintered silver die attach and a 10W/m·K isolation dielectric can reduce thermal resistance compared with certain conventional packaging materials.
  • Half-bridge demonstrators achieved power loop inductance of 1–2nH, voltage overshoot below 2%, and switching speeds approximately six times faster than the evaluated surface-mount reference design.
  • Balanced stackup construction and CTE compatibility play important roles in maintaining microvia reliability.
  • Established PCB fabrication processes can support embedded semiconductor integration, potentially expanding the PCB fabricator’s role in wide-bandgap power electronics manufacturing.
Figure 4. Illustration of a conventional wire-bonded power module showing wire interconnections between semiconductor devices and copper conductors.

Conclusion

Embedded die substrate architectures offer an alternative approach to managing the electrical and thermal limitations of wide-bandgap power electronics. By integrating bare semiconductor dies into thick copper substrates and replacing wire bonds with plated microvias, these constructions can reduce power loop inductance and shorten the thermal path between the semiconductor junction and cooling structure.

Tests of GaN and SiC half-bridge demonstrators reported power loop inductance of 1–2nH, voltage overshoot below 2%, and switching speeds approximately six times faster than the evaluated surface-mount reference design.

The results demonstrate the potential of thick copper embedded die constructions while highlighting the importance of stackup balance, dielectric selection, microvia registration, and thermal interface design. The architecture also illustrates how PCB fabrication processes could support greater integration of semiconductor devices, electrical interconnections, and thermal management within a single substrate.

As switching speeds and power densities increase, PCB fabricators may play a larger role in integrating wide-bandgap power stages, provided that the processes meet the electrical, thermal, and reliability requirements of the intended applications.End of article content

Chris Parker is product engineering manager at TCLAD (tclad.com); chris.parker@tclad.com.