The Case for Copper Pour on Routing Layers
Don’t be afraid of the ground.

Doing special things with a circuit pattern is a hallmark of analog design. All the important signals on the board added together are equal in importance to one net; that net is the ground net. Every active component will have at least one of its pins tied to ground. An RF device could use any number of voltages and will likely want a dedicated power supply for each voltage required. Characteristic impedance relies on a ground plane or two.

Faster digital circuits start to behave like their analog counterparts. The typical routing rules involve fanning out the surface mount pins with short segments and doing the main course of the routing on an innerlayer. An elegant placement could make it possible for the bus of related traces to run entirely on the outer layers.

In that case, we don’t get to sandwich the traces between ground planes to stifle electromagnetic radiation (EMI). The saving grace is we don’t use vias to transition the signals to innerlayers. Printed circuit board design is always a balancing act. We use vias anyway, but in a different way. Wrapping the bus in a full metal jacket on the outer layer and staking the edges of the ground plane to the innerlayer ground is usually sufficient to meet the EMI specifications, where short digital traces are concerned.

When to use caution. Ground pour not accompanied by ground vias can become a conduit for crosstalk between the traces on either side of the ground shape. Removing that copper, leaving the excess air gap, is better than an unsupported metal icicle to serve as an antenna between two lines, whether they are aggressors (noisy) or victims (sensitive to noise).

Count on clocks to be noisy. Receive chains on their way to the input pin are possibly the worst in terms of being a victim. It isn’t always that obvious. Reset lines and other sundry circuits can generate noise. Pretty much any kind of sensor will be a victim, even when the aggressor is routed several layers below the sensing device. Consider the entire board around a sensor to be a no-man’s land in terms of circuits not related to the sensor. As always, read the relevant datasheet application notes regarding layout.

Outer layers. We often label metal layers in a PCB categorically. The outer pair of layers are known as primary and secondary placement layers. The primary placement layer can be top or bottom; it depends on which has the greater number of components. It could also depend on a definition from the physical design team. If the busy side of the board faces downward in the enclosure, it will likely be labeled the bottom but would be considered the primary side.

Wifi to the rescue! close-up
Figure 1. Wifi to the rescue!

No matter the context, the component placement layers offer the best possible location for using a copper flood as a passive heat sink. Through-hole or surface-mount pins can attach directly to a shape. For better solderability, the shape can be defined with a clearance, plus spokes that tie the pin or pad to the outer layer ground planes.

Free reliability through thermal performance. Almost every component on a PCB could generate heat as it does its work. The hottest location in the system is where the chip attaches to the substrate or interposer. The junction temperature at that point determines the lifespan of the component and thus the system. A strong layout provides the thermal path to success.

When the electromagnetic radiation is well shielded, the system’s emissions go down. That effectively reduces power consumption. All your good impedance practices contribute to the efficiency of the power domain. The component doesn’t have to work as hard when there are fewer discontinuities. It’s a little thing that adds up over time.

Uncontrolled thermal excursions can lead to early failure. Early failure leads to warranty work or product replacement on your dime. Fixing or replacing previously sold items cuts into whatever profit margin came from the initial sale. Lower profit leads to all kinds of bad things, ultimately going out of business. Don’t go out of business. Get busy with the planes.

On slots. A technique taught to me at Qualcomm was to break the plane around an external oscillator with a gap that cuts the ground around the device and its posse of resistors. The three sides not connected to the processor are framed by the void. This will help confine the oscillator’s switching noise.

When you’re hot, you’re hot. When your board is hot, that’s not so hot.
Figure 2. When you’re hot, you’re hot. When your board is hot, that’s not so hot. (Source: BigStockPhoto)
You go on vacation, you come back to a well-shielded workstation.
Figure 3. You go on vacation, you come back to a well-shielded workstation.

I always say put in some ground vias near any slots. In this case, this provides an escape path on the next ground plane for all those oscillations to propagate their heartbeat onto some unsuspecting transmission line. Back off on the ground vias a bit on the quiet side of the gap. Maybe even repeat the gap on the first inner (layer 2) ground plane if there are no traces running through there on layer 3. Reroute them if possible so you can trap the noise and corral it back to the device.

Innerlayers. When you flood a layer with significant routing on it, some areas are bound to wind up isolated. The way you group the traces will have a profound effect on the outcome of the ground flood. The first thing I do is set a wider gap rule between the copper flood and traces or shapes.

Backing off will keep the traces from becoming a coplanar line of unknown impedance. I use 0.50mm pull-back, about double what would be typical on the actual ground plane layers. Some busses get 1mm if they are long or have higher data rates. It also helps to set a larger aperture so the copper cannot even get between two traces that are close together.

Managing copper “islands” is a matter of setting a higher threshold for the minimum size. A blob of copper that has a single ground via in it isn’t doing any good. When it comes to power plane layers, there is room for ground pour as well. Let’s say you have a nice frame of ground vias around the perimeter of the board. Pull back the voltage plane and add a frame of ground that joins the stitching vias and completes the Faraday cage around the power planes. Your compliance team will see that and regard you as a saint. Manage it carefully, but don’t be afraid of the ground.

John Burkhert Jr. headshot
John Burkhert Jr.
is a career PCB designer experienced in military, telecom, consumer hardware and, lately, the automotive industry. Originally he was an RF specialist, but is compelled to flip the bit now and then to fill the need for high-speed digital design. He enjoys playing bass and racing bikes when he’s not writing about or performing PCB layout. His column is produced by Cadence Design Systems and runs monthly.