WILSONVILLE, OR – A team from Infinera and Jabil has been selected as designers of the best overall circuit board by a group of industry experts under the auspices of Mentor. (Mentor is now officially Siemens EDA.)

Now in its 28th incarnation, the PCB Technology Leadership Awards recognize engineers and designers who use innovative methods and design tools to address complex PCB system design challenges and produce industry-leading products.

The contest is open to any designs created with Mentor PCB solutions. Judging is based on design complexity and overcoming associated challenges, such as small form factors, high-speed protocols, multi-discipline team collaboration, advanced PCB fabrication technologies, and design-cycle time reduction.

Experts in the PCB industry judged entries from around the world in categories representing computers, blades and servers, memory systems; consumer electronics and handheld designs; industrial control, instrumentation, security and medical applications; military and aerospace solutions; telecom, network controllers, line cards; transportation and automotive designs.

The panel of judges this year included Dr. Rajan Bedi, Stephen Chavez, Mike Creeden, Gary Ferrari, Rick Hartley, Steve Herbstman, Happy Holden, Pete Waddell and Susy Webb. (CD)

Demand for printed circuit boards is going up. But so are production costs.

Raw PCB material pricing has jumped about 40% since June, with the exact increase dependent on material type. This price increase was inevitable and is, in fact, overdue.

During the early months of the Covid crisis, most PCB suppliers were hesitant to pass on their already-increasing material costs. But as China has rebounded faster from the Covid slowdown than the US and Europe, demand for production has escalated. PCB vendors are now more willing to pass higher material costs onto their customers. And the price increases are by no means over.

Not all boards are alike. In fact, no two are exactly the same. That’s kind of the point. We always do something that hasn’t been done before, or we wouldn’t be doing it. The best we can say is many boards share similarities. Just the same, someone in every organization wants to know when the one-off job will be completed.

Often, there is a predetermined schedule in which someone who has never drawn a trace decides when the PCB layout needs to be finished. Such a schedule is usually the result of market forces. It could be back-to-school, CES, or even (especially) a rocket launch date that drives the deadline. Still, it’s not unusual for stakeholders to ask your opinion about the estimated tape-out date.

In this month’s forward-driving column, I glance back at PCEA’s year in “rearview,” which included an energetic jump-start, some challenging air filter retrofitting, some remote diagnostics, and a final refueling at a successful virtual chapter meeting. Next, I hit cruise control and rely on PCEA chairman Stephen Chavez, who focuses on what lies ahead between the vanishing points of highways 2020 and 2021. As always, I’ll also point out some interesting events for you to consider attending.

The past year can be viewed as one of the many good metaphors based on cars and driving, pointing out the differences in size between a rearview mirror and a windshield. You only need to glance in a rearview mirror when backing up or trying to see what may be overtaking you. But if you’re driving forward, your main focus should be on the large, clear windshield to see what’s coming.

The authors of IPC-DPMX, previously known as IPC-2581, have come up with an innovative solution for addressing the needs of the industry for the latest version of the electronics data transfer standard. Developed by the industry, IPC-DPMX has many new enhancements. The just-released Revision C has been reviewed and unanimously approved by the PCB design, analysis and supply chain industry.

IPC-2581B introduced the concept of bidirectional data exchange between design houses and their manufacturing partners. It sought to eliminate the back-and-forth between partners at the very end of the design cycle for communicating and ensuring that critical net impedances were achievable. This communication was important earlier in the design cycle and impacted the layer stack-up, which is hard to change at the end, when design is complete and handed off. Although this innovation was unveiled almost seven years ago, it is still unmatched and unique within an open standard.

In the evolution of silicon implementation, creative solutions to costly problems have become standard practice. One of these solutions is the use of a “chiplet.” A chiplet is precisely what it sounds like: a smaller version of a chip. This doesn’t mean it’s a miniature version. It means that only critical functions that derive significant benefits from a 5 or 7nm fabrication process are included on the chip. Other functions that will work well with 10nm or greater can then be fabricated with appropriate cost savings.

Chiplet technology creates a challenge, however. If all functions were included in the chip, the interfaces could more easily be measured and evaluated. These items now must be accounted for on a package or, more accurately, a system-in-package (SiP) (FIGURE 1). This places greater importance on the electrical characteristics of those interfaces and how that SiP implementation affects that behavior. Thus, there is a need to rapidly assess these issues with minimal effort for maximum results via virtual prototyping.

In late November Marshall Andrews stepped down as the longest-serving head of The High-Density Packaging (HDP) User Group. But as Larry Marcanti assumes the role of executive director of the decades-old electronics consortium, don’t expect big changes.

On Andrews’ 15-year watch, HDP’s membership increased by more than 30 companies, to reach more than 50 total. The ongoing project portfolio rose from five to an average of 25 member-driven activities.

Despite the Covid-19 lockdown, HDP is coming off one of its most successful years yet, having completed 13 projects.

Highly dense electronic assemblies incorporate bottom-terminated components. Miniaturized components create numerous challenges, resulting in a shorter distance between conductors of opposite polarity, solder sphere size reduction, low-standoff gaps, flux entrapment under the bottom termination, blocked outgassing channels, and more significant potential for leakage currents.¹

In the presence of humidity, moisture (mono-layers of water) hydrogen bonds with ionic contaminants to create an electrolytic solution. Ions such as flux activators can dissolve metal oxides present in the flux residue at the soldered connection.² When the system is in operation, the electrical field attraction of the positively charged metal ions migrate to the negative conductor. These metal ions can plate small dendrites, resulting in leakage currents and/or parasitic leakage. As such, ionic residue testing is used to test for problematic residues that could hinder reliable circuit function.³

By almost any measure Universal Scientific Industrial is an EMS behemoth. Yet most of the press surrounding USI over the past few years has been tied to its recent acquisition of AsteelFlash. The deal, completed last month, added 17 manufacturing sites and about $1 billion in topline revenue. For the first time, USI will have sites in the US, Africa and Western Europe.

Today, USI has 27 manufacturing locations in 10 countries, over 24,000 employees and revenue of more than $7 billion. That’s good for the 11th spot in the current CIRCUITS ASSEMBLY Top 50 rankings. There’s no missing the company now.

Yet for all its size, USI could just as easily be recognized for its technical prowess. The company is on the cutting edge of so-called lights-out manufacturing, where few if any staff are found on the factory floor where hundreds of SMT machines run seamlessly, connected by sophisticated software and AGVs feeding the cells on a just-in-time basis.

Two core tenets of Lean manufacturing philosophy are eliminating defect opportunities and minimizing process variation. Consequently, most companies embracing Lean principles do some form of design for manufacturability (DfM) analysis to identify manufacturability issues either during design or in the new product introduction phase. In some cases, this is an automated feature of design software. In other cases, this is done manually.

SigmaTron has adopted a hybrid process that uses software automation to speed basic analysis, followed by an engineering review. This E-DFM software tool reduces the time it takes to create a detailed report from several days to a few hours and works with SigmaTron’s existing Valor software platform.

Bending an organic semiconductor boosts electrical flow. Organic transistors based on single crystals of rubrene can double the speed of electricity flowing through them when a crystal is slightly bent (strained). This behavior cannot be easily achieved with traditional semiconductors made of silicon. Rutgers University researchers found molecules of rubrene are arranged in a herringbone pattern (upper left in figure), forming highly ordered semiconducting molecular crystals that can be used to create rigid or flexible high-performance organic transistors, based on thick or ultra-thin single crystals, respectively. An example of a freestanding rubrene transistor is shown on a fingertip. This method could benefit next-generation electronics. (IEEC file #11946, NASA Tech Briefs, 10/1/20)

Hello, I would like to get some information about your capabilities for Bonepile Rehabilitation. I have some legacy circuit cards that were previously tested on a FACTRON 750. Can you reverse engineer the schematics/gerbers from a known good board? Once you have diagnosis (sic) the problem on a failed board, can you also perform the repair? Are you cybersecurity certified for ITAR data?

This is how an unsolicited customer engagement often begins. No unusual requirements here, other than the obvious need for remedial grammar lessons.

“Yes, yes and yes.”

Good. Then you may be able to assist us. What is your process?

Bonepile rehabilitation and reverse engineering in our world are two different things. When we say bonepile rehabilitation, we are usually talking about troubleshooting boards that have failed, either in the field or in functional/system test, and using the tools we have here at our facility to troubleshoot, repair, and restore them to service. In most cases design documentation (bill of materials, CAD, schematic, Gerber files, etc.) still exist, and are used in this activity, especially to develop test programs (flying probe, JTAG/boundary scan, etc.).

Open connections on area array packages can be difficult to spot, particularly if they are intermittent electrical failures like the examples in FIGURE 1. One or more open joints can occur between the package and solder sphere or at the PCB pad interface. Reflow soldering with either convection or vapor phase can cause packages to move and separate. This can be caused by warping of the package or in some cases minor popcorning due to moisture. Both faults can be simulated and recorded with video for reference.