Electrochemical Reliability
Process Control Plan to Monitor Acceptable Levels of Flux and Other Residues
Because electrochemical failure risk is site-specific, different components need different plans. by BILL CAPEN, JASON EDGAR, DR. MIKE BIXENMAN and MARK MCMEEN
Highly dense electronic assemblies incorporate bottom-terminated components. Miniaturized components create numerous challenges, resulting in a shorter distance between conductors of opposite polarity, solder sphere size reduction, low-standoff gaps, flux entrapment under the bottom termination, blocked outgassing channels, and more significant potential for leakage currents.1

In the presence of humidity, moisture (mono-layers of water) hydrogen bonds with ionic contaminants to create an electrolytic solution. Ions such as flux activators can dissolve metal oxides present in the flux residue at the soldered connection.2 When the system is in operation, the electrical field attraction of the positively charged metal ions migrate to the negative conductor. These metal ions can plate small dendrites, resulting in leakage currents and/or parasitic leakage. As such, ionic residue testing is used to test for problematic residues that could hinder reliable circuit function.3

The core concept for materials compatibility and residue acceptability is a qualified manufacturing process (QMP).4 In a QMP, the manufacturing materials and processes used to produce electronics hardware have been benchmarked and validated against electrical performance in hot/humid conditions. The art of characterizing what chemical residues exist on a manufactured assembly allows an assembler to determine the impact of those residues on electrical performance. The test methodology is useful in developing a risk profile.

After a manufacturing process has been qualified, the next step is to define how to monitor that qualified manufacturing process for ionic residues. The establishment of an ionic process monitoring plan is a requirement for mission-critical, high-reliability electronic products. The sampling plan for ionic residues should be periodic, and with sample sizes such that a manufacturer has confidence, the process is in control.

QFN-88 that failed SIR testing diagram
FIGURE 1. QFN-88 that failed SIR testing.
Failed SIR testing result displayed on graph
FIGURE 2. Failed SIR testing result.
High-Performance Electronic Products
The classification we build products to is IPC Class 3/A. Class 3/A boards call for very stringent manufacturing criteria, since the boards must remain operational in critical conditions. The electronics must provide continued performance and performance on demand. When deployed, there can be no equipment downtime. The products must work correctly every time.

Processes for building the electronics must be qualified and validated. No process residues are accept able. Once validated, there must be a process control plan. Site-specific characterization on components with the highest probability of electrochemical failures is required to ensure every component is reliable.

Materials characterization must be in compliance with IPC J-STD-001 [Rev. F – H] Amendment 1, Cleanliness. Testing requires custom test boards that detect electrochemical reliability across different component designs. Once qualified, there must be a process control plan to monitor for cleanliness on challenging components and processes that are representative of production hardware.

Highly dense electronics are now designed with miniature components. Designs require leadless and bottom-terminated components. These component types create numerous challenges. The problem is these components trap flux residues under the bottom terminations. They are harder to clean. With a tighter pitch, there is a shorter distance between conductors of opposite polarity. Tighter pitch poses a greater risk to reliability.

FIGURE 1 is a QFN-88 component that had partially cleaned flux residues left under the bottom termination after cleaning. Surface insulation testing detected leakage currents. The components were sheared off the board and inspected. Monitoring for these types of defects on high-risk components offers a useful process control method.

Process Control Plan
Temperature-Humidity-Bias (SIR test method) was studied for use in developing a process control plan. Our operations favor electrical resistance measurement methods. The reason: Electrical resistance measurement permits detection of process residues that are both ionic and non-ionic. These process residues are located under the components’ termination and commonly bridge conductor pathways. The residue is not visible to existing process control methods, specifically the resistance of solvent extraction (ROSE). We are looking for process deviations. Is our process consistent lot-to-lot? Is there variability?

IPC pass/fail for SIR testing is 8 Log10Ωs. For this experiment, we decided to build in a margin of safety by setting the lower SIR limit at 8.5 Log10Ω resistance. FIGURE 3 illustrates the mean insulation resistance on a specific component. The lower and upper limit was set from 8.5 Log10Ωs to 12.0 Log10Ωs. The chart shows all 10 boards tested were within the specification range.

Electrical resistance of 8.5 – 12 Log10Ωs.
Figure 3. Electrical resistance of 8.5 – 12 Log10Ωs.
SIR test vehicle
Figure 4. SIR test vehicle.
Research Hypotheses
The following are our temperature/humidity/bias hypotheses:

1. Electrical resistance measurements under bias and elevated environmental conditions are long-accepted quality metrics.

2. The first hours of a test card subjected to temperature/humidity/bias voltage represent the most ionic activity/change.

3. This change can be used to determine the similarity of the process. (Similarly cleaned and produced boards should have similar starting resistance values, end resistance values, and general curve shape.)

4. Deviation in process should be visible as a change.

Test board. QFN-88 and QFN-124 components were selected for this study. A custom SIR test board was designed with the QFNs horizontally positioned in Q1 and Q2. The QFNs were rotated 45° in Q3 and Q4 (FIGURE 4).

The 0.5mm pitch QFN 88 chip is representative of production hardware (FIGURE 5). The tight pitch and large thermal lug are useful in defining cleanliness levels under similar component package styles. This part can be used to test no-clean flux systems for SIR cleanliness levels and to determine whether the cleaning process is capable and efficient in achieving the desired SIR levels for these types of component packages.

The 0.5mm pitch QFN-124 BTC has a dual-row pin-out with ground lug, which makes this particular BTC more challenging than the standard QFN package style, which is a single row around the periphery of the package (FIGURE 6).

Phase 1: Data collection.

  • Perform a series of temperature-humidity-bias tests with the same card to monitor process deviations.
  • Perform ROSE as a direct comparison.
  • Collect the raw data and analyze the data for statistical significance within several blocks of time: first 30 min., first hour, 2 hr., 6 hr., etc.

Phase 2: Process deviation monitoring.

  • Tests must all be run under the same conditions.
    • Ramp speed of the chamber will be a factor, so it will be critical all tests are run with the same chamber.
    • Chamber control feature should be used on a powered-down chamber to ensure all tests start under the same ambient conditions and rise in a similar fashion.
  • Tests must all end at the same time.
    • For this experiment, analyze the data within defined periods.
The SIR testing unit process control module allows the user to create and manage their test boards. Specific fields enable one to set up a particular process control profile. For each channel on the test board, the user can name the profile, and set an upper and lower specification limit. Other settings include time duration, measurement interval, temperature, relative humidity, bias voltage, and measurement voltage.
QFN-88 single row dimensions
Figure 5. QFN-88 single row dimensions.
QFN-124 dual-row component dimensions diagram
Figure 6. QFN-124 dual-row component dimensions.
Data Findings
Twenty test boards were assembled and cleaned using defined process settings. The test boards were subjected to SIR testing using the following settings:

  • Temperature: 40°C
  • Relative humidity: 90%
  • Bias voltage: 5V
  • Measurement voltage: 5V
  • Measurement interval: 5 min.

Results were analyzed over a variety of periods. Baseline ROSE testing was performed on test samples.

FIGURE 7 is a chart of the SIR results for board #11. Channels A&D represented the QFN-88, and Channels B and C represented the QFN-124. The QFN-88 values were below the lower limit, which is not acceptable. The QFN-124 values were acceptable.

In a review of the data, we noticed parallels between the early-stage data and the full 168-hr. data that supported our hypothesis. FIGURES 8 to 11 show the mean data for each of the 4-channels on all 20 test cards in our data set.

Following SIR testing, each of the 20 boards was ROSE tested (FIGURE 12).

SIR test values for board #11.
Figure 7. SIR test values for board #11.
Data Analysis
  • Data was initially plotted in its entirety to look at overall trends.
  • A smoothing function was applied to visualize the trend in the data better.
  • General observations:
    • The dual-row QFN-124 SIR profile appears to be more promising due to a tighter standard deviation.
    • QFN-88 had a relatively uniform spread of data over the range of 7 to 11 Log10Ωs. Many data points were below the lower limits. Clearly, the cleaning process was not properly dialed in to clean this part within the upper and lower specification limits.
    • The higher variation QFN-88 results in a higher standard deviation. A higher standard deviation indicates a lack of consistency with regard to ionic residue present at the signal pins and under the component termination.

FIGURES 13 and 14 represent the average SIR values per hour of testing. The mean and standard deviation were plotted over time (FIGURES 15 and 16). The following observations were made:

  • SIR value tends to start to flatten out around 50 hr.
  • Specific periods had larger variation than others.
  • This is probably noise-related.

Inferences from the data findings. Electrochemical risk factors are not consistent across a printed circuit board; instead, they are specific to components that trap residues under the bottom termination and next to signal pins. The data find different meaningful results between the QFN-88 and QFN-124.

In this study,

  • QFN-88 was harder to clean.
  • There wash higher variability.
  • QFN-88 had many unacceptable results.

Temperature-Humidity-Bias Environment

  • nduces defects from ionic residues on targeted components.
  • Induces defects from non-ionic residues on target components.
  • These defects are reflective of undesirable process deviations.
  • Electrochemical risk is by nature site-specific, rather than an average risk assessment.

Inferences include:

  • The large standard deviations on the QFN-88 component require more work to optimize the cleaning process.
  • Temperature-humidity-bias testing is useful to determine the similarity of the process.
  • A shorter SIR test time can detect process deviations.
  • Contamination is not consistent across the PCB.
  • Some component types are at greater risk of electrochemical failure.
  • ROSE testing is not a predictable method for site-specific testing.
QFN-88 Channel A charts plotted over different time periods.
Figure 8. QFN-88 Channel A charts plotted over different time periods.
QFN-124 Channel B charts plotted over different time periods.
Figure 9. QFN-124 Channel B charts plotted over different time periods.
Research Hypotheses
Hypothesis #1: Electrical resistance measurements under bias and elevated environmental conditions are long-accepted quality metrics. Hypothesis #1 is accepted for the following reasons:

SIR testing is considered the gold standard for detecting ionic contamination. SIR is the best test method for determining the electrochemical reliability of:

  • High-density interconnected board designs populated with miniaturized leadless and bottom-terminated components.
  • Multiple soldering operations that include SMT components on the top and bottom side of the board.
  • Through-hole processes using both wave and selective soldering.
  • Rework and repair operations
  • Conformal coating materials characterization.

Hypothesis #2: The first hours of a test card subjected to temperature/humidity/bias voltage represent the most ionic activity/change. Hypothesis #2 is accepted/rejected for the following reasons:

Accepted: When ionic contamination is present, SIR will be lower at the beginning of the test. The QFN-88 insulatio resistance had lower insulation resistance at the beginning of the test. As the test ran, the insulation resistance improved due to the ionic residue drying out and not being mobile in mono-layers of water present in the humid environment.

QFN-124 rotated 45° Channel C charts plotted over different time periods
Figure 10. QFN-124 rotated 45° Channel C charts plotted over different time periods.
QFN-88 rotated 45° Channel D charts plotted over different time periods.
Figure 11. QFN-88 rotated 45° Channel D charts plotted over different time periods.
Rejected: A short test period does not detect leakage currents and dendritic formations. These typically require longer test time to form and propagate.

Hypothesis #3: This change can be used to determine the similarity of the process. (Similarly, cleaned and produced boards should have similar starting resistance values, end resistance values, and general curve shape.) Hypothesis #3 is accepted for the following reason: The research finds that much can be learned from careful analysis of the first hours of the long accepted SIR test method. The first hours clearly detect process contamination that reduces insulation resistance.

Hypothesis #4: Deviation in process should be visible as a change. Hypothesis #4 is accepted for the following reason: The QFN-88 was clearly different from the QFN-124. Process contamination was detected.

Electrical testing results, with power on during extremes of temperature and humidity, detect the presence of ionic contamination. The challenge industry faces today is the risk factor for electrochemical failures is not the same across a PCB. The risk is site-specific, being more problematic acrossdifferent components.

Process control requires an objective sampling plan for measuring ionic residues of the process. This study looked at two test methods. The ROSE bulk extraction test method is a nondestructive test method that can be used on the actual product. The problem is this method is not consistent in detecting problematic residues across site-specific components.

ROSE testing for each board
Figure 12. ROSE testing for each board.
QFN-124 average per hour chart
Figure 13. QFN-124 average per hour.
QFN-88 average per hour chart
Figure 11. QFN-88 average per hour.
Electrical testing using SIR temperature-humidity-bias is a far superior test method. The problem with this method is it cannot be used on the actual production board. This method requires a test board or coupon that is representative of the complex components used on production hardware. When using a representative test board or coupon, this test method can be used to monitor and control the process with accuracy.

Follow-on research. Follow-on research is needed to develop a “process control plan.” The research team plans to perform a series of tests by first developing the “golden image” to define upper and lower process limits. Using the same test card, the process will be varied to validate the method work for detecting the cleanliness state.

QFN-124 mean and standard deviation averaged every hour chart
Figure 15. QFN-124 mean and standard deviation averaged every hour.
QFN-88 mean and standard deviation averaged every hour chart
Figure 16. QFN-88 mean and standard deviation averaged every hour.
The authors want to thank and show our gratitude to many people who helped make this research possible. Many people behind the scenes executed many of the steps to run this study. The authors acknowledge Anna Ailworth and David Lober for statistically analyzing the data. The authors acknowledge Bobby Glidwell for his design and process control method development using temperature-humidity-bias testing. The authors acknowledge Caroline Spencer, Ph.D., for her work in removing components and imaging. The authors acknowledge the assembly line people who built and cleaned the test vehicles and perform the testing.
Ed.: This article was first published in the SMTA International Proceedings in October 2020 and is republished here with permission of the authors and SMTA. Copyright Honeywell Federal Manufacturing & Technologies LLC, 2021. Notice: This manuscript has been authored by Honeywell Federal Manufacturing & Technologies under contract No.DE-NA-0002389 with the US Department of Energy. The United States Government retains and the publisher, by accepting the article for publication, acknowledges the United States Government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US Government purposes.
  1. IPC-J-STD-001G, Amendment 1, Requirements for Soldering Electrical and Electronic Assemblies, September 2018.
  2. M. Bixenman, V. Sitko and M. McMeen, Qualified Manufacturing Process Development by Applying IPC J-STD-001G Cleanliness Standard, February 2020.
  3. IPC-9202, Material and Process Characterization/Qualification Test Protocol for Assessing Electrochemical Performance, October 2011.
  4. D. Pauls, et al., IPC-WP-019A, An Overview on Global Change in Ionic Cleanliness Requirements, August 2017.
William (Bill) Capen is senior engineering technical specialist at Honeywell FM&T (kcnsc.doe). JASON Edgar is lead electrical engineer at Honeywell FM&T. Dr. Mike Bixenman and Mark McMeen are co-inventors at Magnalytix (magnalytix.com).