PCEA Current Events

Two-Day Talk on EMI Coming to Atlanta

Rick Hartley will present a special live two-day workshop on “Control of EMI, Noise and Signal Integrity in High-Speed Circuits and PCBs” in June in the Atlanta area. As Hartley notes, EMI is a leading concern for electronics designers and a major cause of failures. The seminar has been updated to contain a fair amount of new information that was not taught in years past.

Abstract. When time-varying energy travels in the transmission lines of a printed circuit board, state changing electric and magnetic fields are present. Not properly managed, these fields are the energy source of noise, EMI and signal integrity issues. “Noise” is “intentional energy” that we fail to control and contain. Uncontrolled energy can generate many forms of interference. Some circuits are noisy, others are not. With the right training, the reasons and solutions are easily understood. Compounding the issue are today’s extremely fast ICs. A circuit with 100ps rise time IC outputs can generate very serious problems, whether clocked at 5MHz, 500MHz or 5GHz.

Knowing proper design of circuits and PCBs to contain E&H fields, as well as knowing how to mitigate the effects of high-speed devices, are the keys to successful design of low noise circuits. This two-day seminar is a crisp focus of the issues PCB designers/engineers must know to prevent EMI, signal integrity, crosstalk, ground bounce and grounding issues in high-speed digital and mixed signal designs.

Each attendee will receive a color PDF copy of the full slide deck. For details, click here.

Topics covered include:

Day 1

  • Impact of frequency on PCB layout
  • Frequency – analog vs. digital
  • Where energy travels in circuits
  • Noise, what is it, and why it occurs
  • Impact of proper grounding on noise & EMI
  • Transmission lines and energy return paths
  • Critical importance of proper plane assignment
  • Common misuse of planes
  • Noise and signal attenuation factors
  • Routing and reflections
  • Propagation time and velocity
  • Lumped vs. distributed length lines
  • Transmission line impedance control
  • Impact of nearby traces on impedance
  • Extreme importance of reflection mode switching
  • Routing and termination styles
  • New thoughts on line termination
  • Best line routing styles
  • Impact of long Ts in transmission lines
  • Proper DDR routing
  • VCC and ground bounce
  • Basics of jitter and inter-symbol interference
  • Basics of skin effect and loss tangent
  • Impact of trace corners and vias
  • Crosstalk – what is it, exactly
  • Backward and forward crosstalk
  • Crosstalk critical length
  • Eliminating forward crosstalk
  • Realistic crosstalk levels in circuits
  • Guard traces – good or bad?
  • Differential pair basics
  • Differential pairs in a PCB vs. a cable
  • Differential impedance … what really matters
  • Differential pairs – crosstalk
  • Differential pairs – tight vs. loose coupling
  • Differential pair length matching and skew issues
  • Differential line termination – best approach

Day 2

  • Basic types of EMI
  • Antenna basics and PCB radiators
  • Keys to controlling common mode energy
  • Energy feeding the edge of a plane
  • Solutions to EMI from plane edges
  • Basic component placement issues
  • Board routing to control EMI and noise
  • EMI impact of layer changes when routing
  • Mixed analog and digital PCB design
  • Islands in power / ground planes
  • Routing on ground planes
  • Impact of connector pin assignments
  • Goals for power distribution network (PDN)
  • IC impact on PDN switching noise
  • Importance of low PDN impedance
  • Impact of via and plane inductance
  • Impact on PDN of decoupling location
  • Decoupling boards with routed power
  • Decoupling conventional 4-layer boards
  • Decoupling high-layer-count boards
  • Impact on PDN of IC package inductance
  • Analog IC power decoupling
  • Ferrites in the power bus – good or bad?
  • Extreme importance of PCB stackup
  • PCB stackups that work for SI and EMI control
  • Board stackups to avoid at all cost
  • 4- and 6-layer board stackups that work
  • High-layer-count boards that work
  • I/O filtering and blocking
  • Setup of single ended I/O structures
  • Setup of differential I/O, including ethernet
  • Setup of high frequency differential I/O
  • EMI control in metal and plastic enclosures
  • Slots and openings in enclosures.
  • Proper shielding of cables, low and high frequency.
  • Extreme importance of I/O connector placement
  • Cabling methods to avoid, always!
  • Cables inside the enclosure – good or bad?
  • Potential problems when using chassis as a heatsink
  • Switch mode power supply layout to control EMI
  • Transformer isolated outputs of SMPS
  • Layout of SMPS to minimize EMI
  • SMPS critical circuit loops, including feedback
  • Proper grounding of the SMPS switch node
  • SMPS – secondary methods to control EMI
  • SMPS inductor types and proper mounting

About the instructor. Rick Hartley, retired from L-3 Avionics, is the principal of RHartley Enterprises, through which he consults and teaches internationally. Hartley’s focus is on correct design of circuits and PCBs to prevent and resolve EMI, noise and signal integrity problems. He has consulted with major corporations in the US and 14 other countries. His career has focused on telecommunications, computers and aircraft avionics, as well as medical, appliance and automotive circuits. Hartley has taught seminars at numerous conferences, including the IEEE EMC Symposium, PCB West, PCB East, AltiumLive, Freescale Technology Forum, IPC Apex/Expo and others. He is on the board of directors and the Education Committee of the Printed Circuit Engineering Association (PCEA), a past member of the editorial review board of Printed Circuit Design Magazine and has written numerous technical papers and articles on methods to control noise, EMI and signal integrity, as well as general printed circuit board design techniques. Article ending bug