Connecting the Industry, from Boards to Assemblies

HDP is embarking on new rounds of evaluations of laminates and lead-free solders.
by Mike Buetow

The High-Density Packaging User Group, the nonprofit consortium of electronics manufacturers and suppliers that collaborate on various technical problems in order to reduce cost and time to market, has nearly 25 projects underway, several of which are due to be completed this year.

We spoke in March with Madan Jagernauth, marketing director and project facilitator of HDP, about its current research on lead-free solder alloys, its recent conference Best Papers, and whether the consortium members are ready to tackle artificial intelligence.

The following has been lightly edited for grammar and clarity.

Mike Buetow: It seems like 2024 is something of a transition year for HDP. You had your 30-year anniversary last year. You completed eight projects and you have 18 more now in the implementation phase. Let’s start with the year just ended. As part of your anniversary HDP prepared four special retrospective reports. Can you summarize them and explain why HDP felt it was important to look backward as well as forward?

Madan Jagernauth: Well, Mike, 30 years is a long time for a consortium like this to be operating, so it was important for us to look back to see where we’ve come from and where we’re going. There are lots of challenges in industry. A couple years ago we took a good look at the technical direction in the industry and the kinds of things that HDP should be working on and our members should be paying attention to as the industry evolves.

Looking back was us trying to get a sense of where we’ve come from. In the first decade HDP was a small group, about 15 members on average, so there were a small number of things that could be done. About 20 years ago, with the transition to more environmentally friendly materials, HDP became more important to members and grew to where we are now – about 50 members – and did some really good work starting about 20 years ago in lead-free alloys, some very seminal work on SAC 305 and SAC 405 in the early days, writing implementation guides and those kinds of things. The first thing I looked at was what we did on lead-free solder assessments over the years, and there were some very important sets of projects, reports written and used by our members.

At the time that lead-free solders came on the scene, no materials for lead-free printed circuit boards were really reliable, so the evaluation of laminate materials became very important, to [be able to] say which of these would actually work with higher temperature solders because the reflow temperatures for those lead-free solders were much higher than the reflow temperature for eutectic tin.

Starting about 2006, HDP has been running material evaluations for laminates and we’re on our seventh phase now. That’s the second part of looking back at what material testing we did over time.

And then, of course, there’s all the other associated technologies that evolve over time for printed circuit boards themselves, with microvias, higher density vias and stacked vias, and the assembly technologies of how you actually put components on boards. Those are the four legs that I looked at as I was taking a retrospective and then relating that to how we go forward with our technical direction on the next generation of high-speed materials and evaluating those, the next generation of solders and evaluating those, the higher copper densities and what’s coming with those. With all of this change, what changes are needed to the reliability assessment methodology as you get to things like higher voltages on printed circuit boards for electric vehicles or other types of applications? It all relates back to where we’ve come from, where we are today and where we’re going.

MB: I know that HDP keeps its reports generally in house. They are done by the members for the benefit of the members. Was there any thought given to making the retrospective reports available to a wider audience?

MJ: Yes, those are available on our website. I published a couple of them through LinkedIn. They basically say what we have done. They don’t cover the results of what we’ve achieved.

MB: Let’s talk about the recently completed projects. What highlights can you share about those?

MJ: There’s a lot of work on things like microvia reliability, the way boards stack up and the flatness reports, new technologies like photonic soldering, so a variety of projects were completed last year. We completed eight projects last year. We have 18 in implementation right now. When you look at it, there are six projects related to materials, primarily high-speed materials. There are four projects related to solders, two are related to the reliability of solders themselves and two are to the application of these solders: reflow reliability and rework reliability. There are four projects related to higher copper densities for backdrill, one of them with microvias and two with innerlayer copper balancing, and then there are two or three projects related to different test methodology like next-generation surface insulation resistance testing, one on copper roughness. When I look at the four or five legs of our technical direction, and the fit of the projects to the technical direction, about two-thirds of our projects are in line with where we see the technical direction of the industry pointing. There are of course some projects for which members have very specific near-term issues they’re trying to address and they have commonality with other members, so those get into the mix as well.

MB: HDP has 23 projects underway, and as you noted, 18 in the implementation phase. These projects are approved by the HDP board of directors and going forward are restricted to HDP members and select others that have signed the R&D participation agreements. So implementation really is where the rubber hits the road, so to speak. You mentioned a couple that were recently completed, but you have a few in areas that are constantly evolving, like high-speed materials and next-generation solder alloys. What can you tell us about those?

MJ: We’re in the seventh phase of our materials evaluations right now, which started in 2006. Through Phase 6 we completed evaluations of 85 different laminate materials. Phase 7 is testing of 11 more materials, and this tends to be a two-year project. The completion date is set for 2025 because those running this know that to do a complete set of testing on this set of materials takes a long time. These are major projects that require a lot of member participation and lots of very detailed testing. What was done for that as well is that the test vehicle that was used previously was updated to include new test coupons. That’s very important for our laminate materials suppliers or fabricators. Everybody in the chain is very interested in that project and usually that project gets the highest participation among members because it creates such foundational knowledge for our membership.

Two others I’ll mention [involve] the solder evaluation. We have been evaluating third-generation solders for about eight years; I think the evaluation for third generation started in 2016 and was completed around 2019 or 2020. And this is a collaboration we’re doing with iNEMI. In first phase of this evaluation the thermal cycling was done for 10 minutes dwell times of the two extremes. There were three different thermocycles. There was also some vibration testing done to see if that kind of a test would actually affect the reliability of the solder. That was done three or four years ago.

The second phase started then, and the focus was some of these solders which have to operate for extended durations at high temperature, so there was a desire to test for a longer dwell time. Instead of 10 minutes of the extremes, it was increased to 60 minutes at the extremes, adding essentially 100 minutes per thermal cycling to this process. These are very reliable solders. You had 100 minutes to cycle. It takes it to a much longer cycle. It’s more boring than watching a pot boil. It’s like watching grass grow. But the good news is solders are very reliable. We’re in the middle of that right now.

Then there is a third phase that’s running in parallel that is looking at saying well, there’s a traditional way of thermal cycling that limits the rise time of the cycle. If we did a shock test, would that change the reliability of the material? Would you have the same failure mechanisms and could we substitute a faster rise time to complete this kind of evaluation faster? This is a big part of providing information to our members on the third generation of solders. Some people are still specifying tin-lead. What we’re seeing is this current-generation solders are very reliable but when the testing is done – which I’m sure we will get done to some point – we will see what the results really are that can be published. The intent of course with something as big as this is to publish as much as we can.

MB: How is it decided which materials are included? Does it require participation by the material supplier?

MJ: When we launch a project we will notify all our members and invite them to participate in a project. The ones who want their materials to be part of it, in terms of solders, will say “yeah,” and they will provide materials and which one of their solder compounds they want to evaluate. In the case of Evaluation 3, there was a desire to run a smaller set so that we didn’t have this big matrix. There was a subset of the ones from the second phase of evaluation that went into the third phase of evaluation. Then of course it’s a question of which of our laminate suppliers would participate in providing materials for the test vehicle, [and] which one of our fabricators would fabricate. In this case, the project is led by Richard Coyle from Nokia. Panasonic provided the laminate materials and Sanmina built the test vehicles. And then there’s the usual set of members – Shenju, Nihon Superior, Indium and MacDermid – providing the solders. I may be forgetting one or two.

MB: HDP has received a couple best paper awards of late, one in the area of fabrication and one in assembly. I think nothing better shows the breadth of HDP’s research.

MJ: Our members are doing really good work, Mike. I talked just now about the solder projects and the Evaluation Phase 2. The paper that was presented by [Coyle] at SMTAI last October, titled “A Collaborative Consortia Project to Assess the Effect of Thermal Cycling Dwell Time on the Reliability of High-Performance Solder Alloys,” is the one that we’re doing the 60-minute dwell time on. This is a collaboration between HDP and iNEMI. Testing is being done by Nokia, Collins and CALCE for this particular phase of the project. It’s a big effort across a large number of industry participants who are very interested in the results of this type of testing. And all [Coyle] presented was a status update on where this project is. I came into HDP about three years ago and took over this project and have been working as a facilitator for that period. And we are still in the middle of testing. Not all of the testing is done. The test vehicle is very interesting. It’s got two components on it, a 192-pin BGA, and an 84-pin BGA and as you’d expect the 192-BGA that’s larger fails first and the 84-BGA device sometimes takes forever, especially with the 0° to 100°C cycle, it takes forever to fail.

MB: I really think that this underscores the importance of HDP as a collaborative organization. There is no other organization I can think of that is doing this type of broad-based research with this many members, and consistently producing results. If I go back 30 years, I think most people thought of HDP as a board interconnect organization. As I look over what your research has been over the past several years, nothing could be further from the truth. It really is very broad-based and you’re filling a gap that is badly needed.

MJ: I think what members see is that they can run projects through HDP that they are not able to run themselves efficiently inside of their companies, either because it will take too long or they don’t have the right set of resources all within the four walls. When you look at a project like that one from the material suppliers all the way to the fabricators and the test houses and then you look at the next ones, the ones that will be presented at IPC Apex [in April 2024], those papers are basically another reflection of what we’re doing. The HDP paper that won Best of Conference includes device sizes from 26 sq. mm to 100 sq. mm. Eight different laminate materials, eight fabricators that made these test vehicles looked at the surface topology variations as you look at packet size changes, the way copper is distributed on the various layers, the resin field rates because if you have a high flow versus a low flow resin, it’ll change what happens in ground planes versus via fields.

And then, how do you get to a point of designing something like this where you can actually balance the copper to get the flatness you need to assemble large BGA devices? This is of high interest to many people as they look at larger integrated circuits being put on printed circuit boards and the boards are getting thicker because you’re going to higher-speed devices, more I/Os in the boards … all of this is interrelated. You’ve got what I would say is a highly stochastic system that you’re trying to control. There are many variables in there that I don’t know you can control all of them at any given time. There’s always going to be some variability. But how do you manage it as you gain more knowledge about what you can do in the design to get the results you want? This [paper] is one that was written by Gary Brist and Neil Hubble; Gary is with Intel, Neil is with Akrometrix. This is where the interest is right now.

MB: Have your members asked about starting a project in artificial intelligence?

MJ: No, but I mean, what’s artificial intelligence? Seriously. There are three elements in networks. There’s a compute part, there’s the storage part and there’s a transmission part; networking. Networks are getting faster. The next generation of wireless and optical networks are running at very high speeds. The 1.6 terabit per second network is going to require baud rates of 112Gb. The next-generation wireless networks, they’re talking about sub-terahertz spectrum, from 90 to 300GHz. Try doing that on printed circuit boards. This is where the interest is, so one of the projects we are running now is looking at the effect surface treatments have on high frequency and that will be tested up to 120GHz, I believe, because as you get to those speeds, you’re talking about some major skin effects and when you’ve got an immersion gold or whatever else on top of the copper, where does current actually run? Does this layer of surface treatment affect the performance of that circuit? Things like that are being done right now.

MB: Most of your biannual meetings take place in the US, if memory serves. Your spring meeting this year, which takes place in May, is in Taiwan. Is that unusual?

MJ: Before Covid HDP was doing one [meeting] in North America, one in Asia and when we had a lot of members in Europe, one in Europe. Now we’re doing the annual meeting in February in North America, the spring meeting in May/June in Asia, and then a virtual meeting in the fall.

Ed: HDP’s next meeting takes place May 21-23 in Taipei.

Mike Buetow is president of the PCEA (pcea.net); mike@pcea.net.