RF PCB Layout: Transmission Lines, Impedance and PDN Design

Analog PCB design demands careful attention to power delivery, bypass capacitor placement and impedance control to ensure accurate sensor performance in increasingly compact electronic systems.

The word “analog” has a special connotation in the PCB design world. One of the things that comes to mind is that we measure performance on a linear scale. A specification may call for 100dB of isolation, but achieving even greater isolation is always desirable. The Internet of Things (IoT) could just as easily be called the Internet of Analog Things.

This article will discuss the following:

• How the power delivery network affects analog circuits
• Bypass capacitor placement and routing
• Managing impedance requirements against manufacturability concerns

Sensors come in every flavor under the sun. Measuring heat, light, pressure and anything else in the spectrum falls under the analog umbrella. The smart watch that takes your pulse while sending and receiving radio transmissions from your phone is a good example. The tiny volume of a watch makes it an RF Thunderdome.

One of the greatest challenges in these compact devices is supplying power to the integrated circuits. The process is highly iterative, reducing the power delivery network (PDN) to only what is necessary. Even when additional space is available, excess copper in the power planes can act as an antenna. The design process becomes an exercise in trimming away unnecessary copper to lower the noise floor on transmission lines. Precise power delivery is a hallmark of successful analog design.

A humorous sign once displayed outside a test engineer’s cubicle read, “Relax, it’s all just a bunch of ones and zeroes.” The irony was that the work centered on analog integrated circuits. Board bring-up in the test lab often provided valuable insight into layout decisions, highlighting both successful design choices and areas requiring improvement.

Star routing for the power delivery network. Well-documented schematics play an essential role in analog PCB layout. Detailed notes from the electrical engineer help guide placement and routing decisions. Identifying which components belong within specific shielded areas simplifies placement, while assigning individual bypass capacitors to specific power pins instead of only identifying voltage rails improves routing accuracy.

In some cases, proximity alone is not sufficient. A wide trace may be required to feed the capacitor, followed by a short, narrow connection from the capacitor to its assigned power pin. Multiple pins may share a single capacitor, or several capacitors may be assigned to one pin. Highlighting individual capacitor-to-pin assignments is often more effective than simply color-coding voltage nets.

Although not originally intended for this purpose, the Net Schedule function can also be used to associate bypass capacitors with specific voltage pins. Its primary application is routing emitter coupled logic (ECL), where termination resistors must connect to designated locations. The same approach ensures that moving a capacitor maintains its connection to the intended power pin rather than automatically snapping to the nearest one.

Impedance control – the crux of analog design. Much of analog PCB design revolves around maintaining controlled impedance. A 50Ω transmission line remains the industry standard for many RF applications. Stripline geometry is commonly implemented on the outer layers, where impedance depends primarily on trace width, dielectric thickness and the dielectric constant (Dk) of the laminate material. As a rule of thumb, selecting a trace width approximately equal to the dielectric thickness provides a reasonable starting point before refining the design through calculation.

According to IPC-4101/21, FR-4 has a nominal dielectric constant of approximately 5.4, although the actual value varies by manufacturer and changes with temperature, copper roughness and operating frequency. Standard FR-4 performs well into the 5GHz range in many applications. Beyond that point, lower-loss materials generally become necessary because FR-4 exhibits increasing dielectric loss at higher frequencies.

Impedance mismatch – the bane of signal integrity. Any discontinuity along an RF signal path deserves careful attention. While outer-layer routing is generally preferred for analog signals, placement always dictates the routing strategy. Wherever possible, routing length should be minimized through thoughtful component placement.

The ideal layout places the RF input connector immediately adjacent to the DC blocking capacitor, followed closely by the matching network, typically implemented as a pi network. The amplifier, coupler or subsequent circuit should then connect using the shortest, straightest possible trace with minimal spacing between components.

When additional transmission-line length cannot be avoided, every effort should be made to minimize it through improved placement. Ideally, the components themselves occupy most of the signal path. Excess routing should be avoided because every exposed trace has the potential to radiate energy at the operating frequency and its harmonics.

Considering the trace versus pad width. The PCB stackup can be engineered to support wider controlled-impedance traces. Ideally, trace width closely matches the pad width of common RF components. For example, a pi network constructed with 0201 resistors is best served by a trace width of approximately 0.35mm to match the component pads. Boards using plated through-hole vias typically require a dielectric thickness between 0.3 and 0.4mm from the outer layer to Layer 2.

HDI designs introduce additional complexity. Microvia dimensions dictate dielectric thickness because of laser-drilled via aspect-ratio limitations. If Layer 2 lies only 50µm below Layer 1, maintaining manufacturable trace widths may require clearing Layer 2 beneath the RF trace and instead using Layer 3 as the reference plane.

This routing strategy has been successfully applied in several high-density consumer electronics designs. If Layer 2 remains the reference plane, the resulting trace width may become too narrow for conventional PCB fabrication. Manufacturing would then require extremely thin starting copper and minimal via plating, reducing overall manufacturing robustness and long-term reliability.

Where coplanar waveguides are used. At some point, the transmission line may need to transition into the PCB as a microstrip. Every via introduces an impedance discontinuity that must be carefully managed. One proven approach transitions from stripline to a coplanar waveguide immediately before the signal via.

A coplanar waveguide helps maintain impedance through the transition region surrounding the via, particularly where the reference plane has been cleared around the plated hole. Instead of relying solely on the reference plane beneath the trace, the coplanar waveguide uses grounded copper adjacent to the signal trace to maintain field containment.

Integrating an antenna directly onto the PCB introduces another level of complexity. All copper beneath the antenna should be removed, while multiple rows of stitching vias should surround the antenna region. Staggered rows of interstitial vias, typically three or four rows deep, provide effective isolation. Analog circuits present unique design challenges, but careful layout practices can successfully control their performance.End of article content

John Burkhert, Jr. is a principle PCB designer in retirement. For the past several years, he has been sharing what he has learned for the sake of helping fresh and ambitious PCB designers. The knowledge is passed along through stories and lessons learned from three decades of design, including the most basic one-layer board up to the high-reliability rigid-flex HDI designs for aerospace and military applications. John’s well-earned free time is spent on a bike, or with a mic doing a karaoke jam.