In Case You Missed It

AME Solderability

“Solderability of Additively Manufactured Copper Surfaces”

Authors: Rebecca Wheeling, et. al.

Abstract: As additive manufacturing technology for copper rapidly evolves, the likelihood exists for downstream joining like soldering and brazing. A solderability study was performed to assess process fundamentals over a variety of AM approaches. The solderability of seven different copper (Cu) surface types were evaluated using the wetting balance technique: four Cu coatings (CP-007 and CP-008 conductive copper pastes, IMC-4118 conductive laser sinter paste, IMC-2501 copper ink), two laser-processed Cu surfaces, and one bulk additively manufactured (AM) Cu coupon type. Laser-processed surfaces were subjected to either circular or linear laser raster patterns. AM coupons were fabricated via a powder-bed laser process. In-situ force measurements were recorded while coupons were dipped into and removed from a 63Sn37Pb (SnPb) or 96.4Sn3.0Ag0.6Cu (SAC 305) solder bath, permitting contact angles and surface energies to be calculated. Meniscus height values were also measured. Surfaces were characterized before and after dipping via optical and electron microscopy. Results conclusively indicated that although all samples were intended to represent pure Cu, wettability was found to be strongly dependent on surface type with several samples exhibiting no wetting. Although the CP-007 paste performed the best of any nontraditional surface, all nontraditional surfaces saw significant wettability improvements with aggressive cleaning via HCl etching. (Journal of Surface Mount Technology, October 2023, https://doi.org/10.37665/smt.v36i3.32)

Routing

“A Novel Global Routing Algorithm for Printed Circuit Boards Based on Triangular Grid”

Authors: Jiarui Chen, et. al.

Abstract: Global routing plays a crucial role in printed circuit board (PCB) design and affects the cost of the design significantly. Conventional methods based on rectangular grids have some limitations, whereas this paper introduces a new algorithm that employs a triangular grid model, which offers a more efficient solution to the problem. First, the authors present a technique to sort all unconnected two-pin nets. Next, a triangular grid graph is constructed to represent the routing resources on the printed circuit board. Finally, the authors use the concept of maximum flow to identify the paths for global routing and apply detailed routing for the completion of wires. Results from experiments demonstrate that the authors’ algorithm is faster than two state-of-the-art routers and does not have any design rule violations for all industrial PCB instances. (Electronics, December 2023, https://doi.org/10.3390/electronics12244942)

Thermal Conductance

“Material Characteristics Governing In-Plane Phonon-Polariton Thermal Conductance”

Authors: Jacob Minyard and Thomas E. Beechem

Abstract: The material dependence of phonon-polariton-based in-plane thermal conductance is investigated by examining systems composed of air and several wurtzite and zinc-blende crystals. Phonon-polariton-based thermal conductance varies by over an order of magnitude (⁠∼0.5–60nW/K), similar to the variation observed in the materials corresponding to bulk thermal conductivity. Regardless of the material, phonon-polaritons exhibit similar thermal conductance to that of phonons when layers become ultrathin (⁠∼10nm), suggesting the generality of the effect at these length-scales. A figure of merit is proposed to explain the large variation of in-plane polariton thermal conductance that is composed entirely of easily predicted and measured optical phonon energies and lifetimes. Using this figure of merit, in-plane phonon-polariton thermal conductance enlarges with increases in 1) optical phonon energies, 2) splitting between transverse and longitudinal mode pairs, and 3) phonon lifetimes. (Journal of Applied Physics, October 2023, https://doi.org/10.1063/5.0173917)

Thermal Performance

“Thermal Modeling of Hybrid Three-Dimensional Integrated, Ring-Based Silicon Photonic–Electronic Transceivers”

Authors: David Coenen, et. al.

Abstract: Co-packaged optics for high performance computing or other data center applications requires dense integration of silicon photonic integrated circuits (PICs) with electronic integrated circuits (EICs). This work discusses the impact of three-dimensional (3-D) hybrid integration on the thermal performance of Si ring-based photonic devices in wavelength-division multiplexing PICs. A thermal finite element model of the EIC-PIC assembly is developed and calibrated with thermo-optic device measurements, before and after integration of an electrical driver on top of the PIC by means of microbump flip-chip bonding. Both measurements and simulations of the thermal tuning efficiency and crosstalk between silicon photonic devices show that the EIC can have a significant impact on the thermal performance of the integrated heaters in the PIC by acting as an undesired heat spreader. This heat spreading lowers the heater efficiency to 43.3% and increases thermal crosstalk between the devices by up to 44.4% compared with a PIC-only case. Finally, it is shown that these negative thermal effects of 3-D integration can largely be mitigated by a thermally aware design of the microbump array and the back-end-of-line interconnect, guided by the calibrated thermal simulation model. (Journal of Optical Microsystems, December 2023, https://doi.org/10.1117/1.JOM.4.1.011004)