Technical Abstracts

In Case You Missed It


“PCB Defect Detection Algorithm Based on CDI-YOLO”

Authors: Gaoshang Xiao, et. al.

Abstract: Existing deep learning-based PCB defect detection methods are difficult to simultaneously achieve the goals of high detection accuracy, fast detection speed, and small number of parameters. Therefore, the authors propose a PCB defect detection algorithm based on CDI-YOLO. First, the coordinate attention mechanism (CA) is introduced to improve the backbone and neck network of YOLOv7-tiny, enhance the feature extraction capability of the model, and thus improve the accuracy of model detection. Second, DSConv is used to replace part of the common convolution in YOLOv7-tiny to achieve lower computing costs and faster detection speed. Finally, Inner-CIoU is used as the bounding box regression loss function of CDI-YOLO to speed up the bounding box regression process. The experimental results show that the method achieves 98.3%mAP on the PCB defect dataset, the detection speed is 128 frames per second (FPS), the parameters are 5.8M, and the giga floating-point operations per second (GFLOPs) is 12.6G. Compared with the existing methods, the comprehensive performance of this method has advantages. (Nature, March 2024,


“Review of Methods for PCB Panel Depanelization and Methods for Correct Assembly of Electronic Components on PCB Panels”

Authors: Mateusz Łyczek and Wojciech Skarka

Abstract: Currently, processes related to PCBs, such as depanelization and checking the correct functioning of the boards, are carried out in separate devices. The authors review the literature and analyze trends related to these aspects of PCB panel manufacturing. The purpose of this analysis is to indicate the currently used depanelization methods and methods for checking the correctness of the assembly of electronic circuits on PCB panels. The publications were found in such knowledge bases as Scopus, IEEE Xplore or Emerald insight. In the following article, a systematic literature analysis along with a mapping study is used. This publication provides a review of selected scientific papers found in the above-mentioned databases. Based on these analyses, insights related to future work on both aspects of PCBs were presented. These insights are part of the development of new integrated devices for depanelization and verification of PCBs. (Electronics, March 2024,


“Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model”

Authors: Suwan Kim, et. al.

Abstract: Resolving the design rule checking (DRC) violations at the pre-route stage is critically important to reduce the time-consuming design closure process at the post-route stage. Recently, noticeable methodologies have been proposed to predict DRC hotspots using machine learning based prediction models. Little attention has been paid to how the predicted DRC violations can be effectively resolved, however. The authors propose a pre-route DRC violation resolution methodology that is tightly coupled with fully compatible prediction model. Precisely, the authors devise different resolution strategies for two types of DRC violations: 1) pin accessibility (PA)-related and 2) routing congestion (RC)-related. To this end, the authors develop a fully predictable ML-based model for both PA and RC-related DRC violations, and propose completely different resolution techniques to be applied depending on the DRC violation type informed by the compatible prediction model such that for 1) PA-related DRC violation, the authors extract the DRC violation mitigating regions, then improve placement by formulating the whitespace redistribution problem on the regions into an instance of Bayesian Optimization problem to produce an optimal cell perturbation, while for 2) RC-related DRC violation, the authors manipulate the routing resources within the regions that have high potential for the occurrence of RC-related DRC violations. Through experiments, it is shown that the authors’ methodology resolves the number of DRC violations by 26.54%, 25.28%, and 20.34% further on average over that by a conventional flow with no resolution, a commercial ECO router, and a state-of-the-art academic predictor/resolver, respectively, while maintaining comparable design quality. (ISPD ’24: Proceedings of the 2024 International Symposium on Physical Design, March 2024,

Flexible Electronics

“Density Functional Theory of Straintronics Using the Monolayer-Xene Platform: A Comparative Study”

Authors: Swastik Sahoo, et. al.

Abstract: Monolayer silicene is a front runner in the two-dimensional (2-D)-Xene family, which also comprises germanene, stanene, and phosphorene, to name a few, due to its compatibility with current silicon fabrication technology. Here, the authors investigate the utility of 2-D-Xenes for straintronics using the ab initio density functional theory (DFT) coupled with quantum transport based on the Landauer formalism. With a rigorous band structure analysis, the authors show the effect of strain on the K-point and calculate the directional piezoresistances for the buckled Xenes as per their critical strain limit. Further, the authors compare the relevant gauge factors (GFs) and their sinusoidal dependencies on the transport angle akin to those of silicene and graphene. The strain-insensitive transport angles corresponding to the zero-gauge factors for silicene and germanene are 81° and 34° for armchair (AC) and zigzag (ZZ) strains, respectively. As the strain limit is increased to 10% in stanene, there are notable changes in the fundamental parameters, which entail a change in the critical angle along the armchair (69°) and zigzag (34°) directions. The small values of gauge factors can be attributed to their stable Dirac cones and strain-independent valley degeneracies. The authors also explore conductance modulation, which is quantized in nature and exhibits a variation pattern similar to that of other transport parameters against applied strain. Based on the obtained results, the authors propose the buckled Xenes as an interconnect in flexible electronics and as promising candidates for various applications in straintronics. (ACS Applied Nano Materials, January 2024, ending bug