In Case You Missed It

PCB Fabrication

“Next-Generation Printed Circuit Boards Manufacturing: An Innovative Numerical Investigation Using Electroforming Process”

Authors: Ilhem Boutana, et al. 

Abstract: Electroforming emerges as a pivotal and cost-efficient technology, transforming products not only by enhancing their resistance to corrosion but also by elevating their aesthetic appeal. This process applies a precisely controlled metal layer onto a substrate through electrodeposition, yielding a robust, visually striking finish. In this paper, the authors unveil a cutting-edge modeling approach for simulating the electrodeposition process in printed circuit board (PCB) manufacturing, leveraging the capabilities of COMSOL Multiphysics: Electrodeposition Module. The innovative methodology involves a thorough investigation of how varying process parameters influence the deposition’s weight and thickness, thereby ensuring the precision and reliability of numerical simulations. (Advanced Manufacturing Technologies, April 2025)

 

Semiconductors

“Three-Dimensional Transistors with Two-Dimensional Semiconductors for Future CMOS Scaling”

Authors: Arnab Pal, et al.

Abstract: Atomically thin two-dimensional (2-D) semiconductors – particularly transition metal dichalcogenides – are potential channel materials for post-silicon complementary metal–oxide–semiconductor (CMOS) field-effect transistors. However, their application in CMOS technology will require implementation in three-dimensional (3-D) transistors. Here the authors report a framework for designing scaled 3-D transistors using 2-D semiconductors. The approach is based on non-equilibrium Green’s function quantum transport simulations that incorporate the effects of non-ideal Schottky contacts and inclusive capacitance calculations, with material inputs derived from density functional theory simulations. A comparative performance analysis of different 3-D transistors (2-D and silicon-based) and channel thicknesses is carried out for both low-standby-power and high-performance applications. This suggests that trilayer tungsten disulfide is the most promising material, offering an improvement in energy-delay product of over 55% compared with silicon counterparts, potentially extending CMOS scaling down to a few nanometers. They also show that 2-D semiconductors could be uniquely engineered to create 2-D nanoplate field-effect transistors that offer nearly tenfold improvement in integration density and drive current over both 2-D- and silicon-based 3-D field-effect transistors with similar footprints. (Nature Electronics, vol. 7, Dec. 16, 2024)

 

Quality Assurance

“A Novel PCB Surface Defect Detection Method Based on Separated Global Context Attention to Guide Residual Context Aggregation”

Authors: Lingyun Zhu and Renyan Zhao 

Abstract: In the production and manufacturing of printed circuit boards (PCBs), defects can have a negative impact on both product performance and usability. To tackle the issue of false detections stemming from a high volume of small defects and complex backgrounds in PCBs, the authors propose SRN_Net, an innovative small object detection framework specifically designed for PCB defect identification scenarios. First, an advanced separated global context attention (SGC) mechanism is introduced to enhance the model’s attention to small targets and improve the detection accuracy of the model for small targets. Further, a residual context aggregation (RCA) module is seamlessly integrated into the network’s neck, effectively attenuating the disruptive influence of irrelevant background noise during the fusion of small target features. Last, a no-stride convolution (NSC) technique is deployed in both the trunk and neck of the network and meticulously designed to enhance small target detection accuracy by minimizing feature loss during the convolution process. Extensive experiments on the PCB dataset demonstrate that, compared to state-of-the-art algorithms, SRN_Net achieves increases of 1.1% in precision, 1.3% in recall, 0.6% in mAP@0.5, and 4.6% in mAP@0.5:0.95, highlighting its superior performance in defect detection. To demonstrate the efficacy of SRN_Net across other industrial datasets, the authors conducted an additional evaluation on the NEU surface defect dataset, achieving an mAP of 75.8%. This work contributes to advancing small object detection accuracy and robustness in practical applications. The code will be available at https://github.com/Zhaohuohuo666/SRN. (Scientific Reports, March 20, 2025) 

 

“Reliability Analysis and Parameter Optimization of Board-Level BGA Packaging Structures under Thermal-Drop Impact Load”

Authors: Yanxi Sun, et al.

Abstract: As electronic products become more pervasive, instances of their unintentional dropping during periods of high-power consumption are becoming increasingly prevalent. Thermal loads can induce fatigue damage in the solder joint material, whereas drop impact loads can instantaneously impose substantial mechanical stresses. Consequently, the purpose of this paper is to investigate the mechanical behavior of solder joints when subjected to the concurrent effects of heat and drop impact loads. In this work, a 3-D finite element model of a board-level ball grid array (BGA) package structure is established, and numerical calculations are performed based on thermal-drop impact load sequence coupling. The effects of chip thickness, solder ball height, diameter and array on its temperature field distribution, solder ball stress and average impact life are investigated. Optimization schemes were designed using Taguchi quadrature and surface response methods. The optimal combination of structural parameters to minimize solder ball peeling stress was obtained by mathematical-statistical analysis and regression analysis. (Soldering & Surface Mount Technology, April 2025)