SerDes Verification with Hundreds of High-Speed Channels

A progressive, automated verification approach enables engineers to analyze hundreds of high-speed channels in hours instead of days.

Most verification tools and workflows in the market today are designed to analyze only a handful of links at a time. This creates a dangerous gap: when you can verify only a small subset of channels, the chance is real you’ll miss the specific links that have critical signal integrity issues. Traditional post-layout verification workflows simply don’t scale when dealing with 100+ channels that require comprehensive compliance verification.

The only way to be 100% sure is to verify all channels. Absent the right approach or tools, this tedious task will consume a lot of time and effort. In this column, we will discuss a progressive verification approach that automates post-layout verification across all channels and finally accelerates the process to hours.

Figure 1. A PCB layout with significant signal routing violations.

What Limits the Verification of All Channels?

A single server board can contain 300+ PCIe 5.0 channels running at 32GT/s or higher. For each channel, engineers must identify critical 3-D areas, create individual 3-D solver projects with precise port and boundary configurations, run hours-long electromagnetic simulations, export and assemble S-parameters combining 2-D and 3-D models, configure TX/RX equalizers according to complex protocol specifications and, finally, perform compliance analysis while iterating on failures.

To put this into perspective, a dual-socket server board that contains 336 PCIe 5.0 channels, for example, requires around 39 hours of runtime, plus days (or even weeks) of manual setup work. This fundamentally custom, intensely manual workflow demands signal integrity specialist expertise at every step, making it impractical to analyze anything other than a few channels.

Figure 2. A server board with 336 PCIe 5.0 channels.

Progressive verification. Progressive verification is a critical strategy that enables engineers to find potential problems as early and as easily as possible in the design cycle, when fixes are least expensive and most impactful. By structuring the workflow so that modeling accuracy and analysis time increase progressively with each stage, teams can quickly eliminate obvious issues using fast, simple checks before investing in time-intensive, high-fidelity simulations. This approach defers expertise-intensive analysis until it’s truly needed, rather than wasting time on problems that could have been caught with basic verification.

Figure 3. Post-route SerDes verification flow.

The approach starts with electrical DRC during layout to catch common problems early. Next, standards compliance analysis examines the system-level interconnects to verify that protocol requirements are met. Finally, after eliminating as many issues as possible at these preliminary stages, IBIS-AMI or vendor-based model simulation predicts actual system performance with real devices and settings.

An automated alternative. The HyperLynx post-route verification transforms this expertise-intensive process into a simple workflow through Python-based automation, with two analysis approaches.

The SerDes Compliance Wizard runs model-free protocol analysis and focuses on protocol-specific compliance testing without requiring IBIS-AMI models. It compares these models against over 200 SerDes protocol standards and variants to verify that each channel meets the required electrical and timing specifications, enabling faster, simplified verification.

The SerDes Batch Wizard, which runs comprehensive analysis using IBIS-AMI models, incorporates transmitter and receiver behavioral models to provide more detailed channel simulation with equalization effects. This approach is suitable for complete end-to-end channel verification with realistic component behavior, including TX/RX equalization.

Split flow. To speed verification, large-scale compliance runs can be accelerated by running simulations in parallel, reducing turnaround time. While automation eliminates manual effort, split flow analysis addresses the computational bottleneck that remains.

Figure 4. Split flow divides the design into multiple electrically independent “mini boards.”

For example, in Figure 4, a 336-channel design might be split into four sections, all running simultaneously on different CPU cores or different servers entirely.

The performance gain is dramatic when compared to traditional methods:

Traditional GUI-based flow: 39 hr.
Automated split flow: 7.66 hr.

This provides a 5.1x speed increase (an 80% time reduction) without compromising on the number of verified channels.

Another Real-World Case Study

A Siemens SDB-56G design features an adaptive SoC with 112 QSFP-DD and SFP-DD channels targeting 56Gb/s, with a stretch goal of 112Gb/s, to demonstrate the power of split flow for rapid design evaluation.

The design team wanted to explore two sets of drill size alternatives at 56Gb/s first, so they comprehensively analyzed all 112 channels, modeling 192 3-D structures and generating automated reports in just 3.5 hr. The results showed that one drill size provided 103% better eye height and 4% better eye width, a decision that could be made in one afternoon rather than weeks of traditional analysis. The team then validated all channels at 112Gb/s, identified passing channels and outliers that required optimization, all in under 6 hr.

The key advantage: Switching between design alternatives required editing only control files and then clicking “Run,” with complete modeling, analysis, and reporting executed automatically overnight.End of article content

Sajeda Tamimi is product marketing manager at Siemens. PCD&F/CIRCUITS ASSEMBLY shares this column each month as a benefit to its corporate customers and to provide real-world help to its members.

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