Stackup Decisions That Prevent EMI Problems Later

A seemingly harmless low-speed feedback trace caused an 18dB emissions failure, demonstrating why stackup reviews must account for high-impedance nets and return paths.
by Ujjwal Datt Sharma

Designers make stackup decisions during the initial stages of PCB layout, but the consequences often emerge later in the electromagnetic interference (EMI) laboratory. Layer count, copper weight and component placement rank among the most expensive design elements to change after fabrication.

This article examines an early design mistake on a high-speed PCB. The engineering team evaluated the design during planning, but the board ultimately failed electromagnetic compatibility (EMC) pre-compliance testing. The root cause offers a lesson for high-speed design engineers who may overlook a fundamental principle while managing competing design and debugging tasks.

The board was a typical server-grade motherboard of the kind high-speed design engineers encounter regularly. It included a field-programmable gate array (FPGA), CPU, Ethernet switch application-specific integrated circuit (ASIC), multiphase voltage regulators and low-dropout regulators (LDOs).

The design used a 26-layer stackup, Megtron-class dielectric material and six signal layers, including the top and bottom layers. The layout followed conventional design practices. Low-speed signals occupied the outer layers, while high-speed differential pairs used stripline routing between reference planes. The planes above and below the high-speed signal layers provided return paths and helped contain electromagnetic fields.

The failure. The board failed radiated emissions testing by 18dB, with the primary problem occurring near 200MHz. Voltage regulator tuning did not cause the failure. Instead, common-mode noise escaped the PCB through external cabling.

The failure originated in the board’s physical design, and a more thorough stackup and routing review could have identified the risk before fabrication.

The emissions-versus-frequency plot showed a peak near 200MHz, indicating that common-mode current coupled into the external cables and caused excessive radiation. This behavior represents a typical EMC pre-compliance failure.

The high-speed signal traces did not cause the emissions problem. Their stripline arrangement provided appropriate reference planes and electromagnetic field containment.

The actual problem escaped attention during stackup review because the team did not classify the affected net as a high-speed signal.

Root cause. The failure originated from a 15kΩ resistor connected to a complex programmable logic device (CPLD) feedback pin. The layout placed the resistor at the end of a long trace on the top layer.

Design reviews often overlook resistor dividers connected to feedback pins because engineers classify these nets as low-speed signals. The DC current through the 15kΩ resistor was approximately 100–200µA, and the design did not require controlled impedance for the trace.

However, switching noise from a nearby voltage regulator coupled into the long feedback trace. Oscilloscope measurements revealed the resulting common-mode noise, which subsequently coupled into the external cables.

At approximately 200MHz, even a trace measuring only a few centimeters can represent a significant fraction of a wavelength.

The calculations demonstrate how an early layout decision can create a significant EMC problem. Although the feedback trace carried a low-speed signal, its physical dimensions made it susceptible to radio frequency (RF) coupling.

At approximately 200MHz, a quarter-wavelength in Megtron-class dielectric material can approach 20cm, depending on the effective dielectric constant. A 3-4cm trace therefore represents a meaningful fraction of that length.

A PCB trace may exhibit approximately 10nH/cm of parasitic inductance, depending on its geometry and return path. In this case, the estimated trace inductance reached approximately 35nH.

The switching regulator’s MOSFET output capacitance (Coss), along with associated parasitic capacitance, contributed an estimated 18pF. Although the regulator operated at a switching frequency of 500kHz, its fast switching transitions excited higher-frequency behavior in the circuit.

The estimated inductance and capacitance formed a resonant circuit.

Using the LC resonance equation: f = 1 / (2π√LC)

With L = 35nH and C = 18pF, the estimated resonant frequency reaches approximately 200MHz. This calculated frequency closely matched the emissions peak during EMC pre-compliance testing.

The respin. The engineering team made two primary layout changes during the board respin.

First, the team moved the feedback divider network closer to the feedback circuit, reducing the trace length from several centimeters to a few millimeters.

This change eliminated the long trace that had acted as an unintended antenna. Rather than simply reducing the noise amplitude, the modification removed the primary coupling mechanism. Second, the team separated high-speed signal return paths from areas containing dense voltage regulator via structures.

A high-current voltage regulator on a server-grade motherboard can deliver up to 250A. Its layout typically uses numerous vias to distribute current and manage thermal performance.

These vias and their associated antipads can interrupt nearby reference planes and force high-frequency return currents to follow longer paths. The team moved high-speed traces away from these via-dense regions to preserve continuous adjacent reference planes and minimize return-current loop areas.

This approach reduced the need for return currents to detour around large antipads and other plane discontinuities.

The revised board passed EMC pre-compliance testing, although the remaining margin was narrow. The redesign resolved the original 18dB emissions failure, and the team planned additional margin improvements for the next stackup revision.

New Considerations for Stackup Reviews

Designers should evaluate any potentially noise-sensitive net as an RF coupling path, regardless of its nominal operating frequency.

Feedback dividers, sense lines, enable pull-ups and other high-impedance connections can become susceptible to switching noise when long traces expose them to nearby electromagnetic fields.

Whenever practical, designers should place these components within a few millimeters of their destination pins. The critical question extends beyond how much current a voltage regulator carries. Engineers must also consider what happens to the switching energy that couples into surrounding circuitry.

In this design, the high-speed traces followed established routing guidelines. The internal reference planes provided shielding that helped contain electromagnetic fields, much like a Faraday cage. However, the emissions problem originated on an outer layer, where the design routed low-speed signals.

Outer-layer routing therefore deserves the same scrutiny as internal high-speed routing, particularly when those signals connect to high-impedance nodes or interact with circuitry near the chassis boundary.

Designers should also review the fabricated stackup rather than relying exclusively on nominal design values.

Heavy copper on internal power planes can affect lamination behavior and dielectric thickness through the board’s Z-axis. These variations can influence the finished impedance of high-speed transmission lines.

Before approving a stackup, engineers should verify the fabricator’s core and prepreg thicknesses against the impedance requirements and confirm that the finished construction supports the intended transmission-line geometry.

Conclusion

The 26-layer stackup performed as intended for the board’s high-speed signal routing, but the design review failed to identify a vulnerable low-speed feedback trace.

Although the internal reference planes contained the high-speed signals, the board still exceeded the radiated emissions limit by 18dB because common-mode noise coupled into external cabling.

The failure demonstrates that stackup design and net placement must work together. Engineers cannot rely on reference-plane shielding alone while overlooking high-impedance signals on outer layers.

A thorough review should consider not only high-speed routing and impedance control but also the placement, length and electromagnetic exposure of sensitive low-speed nets. Otherwise, the engineering team may discover these problems only after the board reaches the anechoic chamber.
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Ujjwal Datt Sharma is a hardware engineer working on high-speed board design, power delivery, and system validation for data center hardware. The board described is from independent research; ushar1@unh.newhaven.edu.