designer’s notebook
John
Burkhert, Jr.

PCB Design Strategies: Designing for High-Pin Count Devices

Routing and fanout strategies for high-pin-count devices, from managing dense BGA escapes to maximizing available routing layers.

As devices shrink in pitch and increase in pin count, current density becomes a concern. The outer rows of the devices typically have many signal pins, while the pins in the center focus on power and ground. At the edges, the first few layers of the board must be used specifically for fanout.

Figure 1. Just an average 1,369-pin FPGA using a 1.27mm (0.05″) pitch. In terms of colors, green is the primary ground domain. Deep purple represents where heavy metal is needed for high current. The lighter magenta is a lower-wattage, more spacey kind of metal, like Pink Floyd, and the orange? Well, orange you glad those are the no-connect pins?

One of the worst approaches when faced with a BGA of 1,000 pins is to drop a via deep into the board for pins on the edge of the device. Every routing channel on the first three layers may be needed, with layer 2 routed in the air gaps of the other two.

The point is to get away from the device until the trace has a chance to join the normal flow of the routing channels. There are two distinct areas. One is the fanout zone, followed by everything else, where up, down, left and right make sense.

Figure 2. The first step is to address the outer ring(s), using the top layer to escape to a via for an internal routing layer or to a nearby component placed there for that reason. The arrows indicate the fanout flow: always away from the core. For the sake of rework, as well as room for the fanout, a component-free area around the device makes desoldering easier if the device needs to be replaced. Otherwise, the technician has to remove the nearby components first. (Figures 2-7 credit: Author)

Find the beach and drop a via that reaches a level where the current is going the right way. Until the vast majority of the connections are handled in that manner, it makes no sense to route between component clusters. Fanout occurs early in the timeline, and updates to the schematic are probably still on the table. It is much easier to move or edit a group while it remains isolated from the rest of the board.

The outer ring of pins should be routed to “anywhere but here” using the outer layer of the board. If there is room to route between the pins, the second ring of pins should escape on the outer layer as well. If there is no room for that, as with a 0.4mm pitch, the next layer down is best, even if that is the traditional ground layer.

Conventional wisdom calls for routing orthogonal to the traces on adjacent layers. In reality, that is a nonstarter on the edges of a pin field. The routing direction should radiate away from the center of the device far enough to reach a component conveniently placed around the device or a via where the regular routing scheme can begin according to each layer’s purpose.

Figure 3. This trace in red is consuming too many vertical routing channels. One option is to drop a via in the upper-left corner and wrap around the differential pairs on the horizontal routing layer. The other option is to use the same brown layer throughout and follow the arrows on the right side, routing under the FPGA to the point where only two traces pass through the fanout vias. From there, the routing goes all the way around the high-speed lanes. The first option seems like less work.
Figure 4. The strategy around horizontal and vertical routing layers involves knowing when to break away from the trend. The little box full of dangling lines has enough lanes to proceed with a minor revision to the trace. Obstacles such as shields, slots and board edges can provide places to route counter to the prevailing directions as a matter of necessity.

If a PMIC device has external oscillator pins, they are likely buried deep inside the BGA pin field rather than out on the perimeter where they would be preferable. There may not be enough headroom for a crystal on the opposite side of the board, requiring some internal routing to reach the crystal.

If that is the case, a guard band around those traces is appropriate. Like almost every other component, there is a good reason to place the PMIC near the SoC. It is the same reason a single regulator is placed near the pins that use the power it provides to a chip. It is a source of signal degradation that should be minimized. In the case of a PMIC, there are a number of such concerns.

With the power domains and essential routing complete, the schematic can finally be closed and the remaining connections routed using the two inner layers for up/down and side-to-side routing channels. There are no length or width requirements left for the unrouted segments. The average person might assume this is the nature of most, if not all, routing solutions. This has become less common as the percentage of constrained nets has grown over time.

Figure 5. Both power domains can be connected without overlap. If it was not obvious before, it is now clear that the two main power domains can be supplied with shapes on this layer based on the routing study. The shapes will fill in to distribute the voltages with minimal neck-down. (As dynamic copper would most likely be used for the power planes, the traces would remain as a backbone. Though they are not even close to sufficient in terms of width, they will prevent a future trace from splitting the plane entirely in case additional routing ends up on this layer.)

Closing those last traces can be a chore, as all the good routing channels seem to be taken. There are times when the routing goal is “anywhere but here.” Routing can begin at both ends, with a meander extending as far as possible in any direction. Along the way, it may be necessary to be “impolite” with the existing work. If the two ends can cross at some point, the routing solution is only a via away. On a 95% routed board, that still may be a problem. I remember spending 20 minutes clearing space to add one ground via. Such is life under an NFC chip in a phone.

The fanout provides a chance to make minor adjustments to the placement. This effort continues throughout the fanout and routing steps. There is always some guesswork involved in making design decisions. The decisions are not always right, but adjustments can always be made when new information comes to light.

Figure 6. Re-examining this unused MIPI corner gets two more vias out of the grid. If only one trace can be routed between pins/vias, that space should be used. Routing a trace through every gap can depressurize the inner layers in the same way. This applies to pin-grid connectors as well as BGA devices. Maximizing the number of connections on each layer helps reduce the layer count to something more feasible.

Let’s Talk About Preliminary Routing

Cross-probing and selectively displaying or colorizing nets provide insight into what is to come. Even after checking off on the placement gate, it is a good idea to maintain elasticity for as long as possible. Modularity is useful when the inevitable update makes it necessary to relocate or rotate a device and its constituent parts.

That said, the various devices have to be connected at some point. The heaviest-hitting device on the board is a good place to start. It could be key because it uses the most power or has the most interconnects. It may also be the main amplifier or whatever motivates the product. Some device lies at the heart of every board, so that is where risk management begins. The process has to start somewhere.

Step one is the highest-priority net on the highest-priority chip. It is all downhill from there, working toward the least significant connections. Operationally, pull-up resistors may not even need to be placed until the pin escape from the device is complete. Once the trace is fanned out and routed to a clear spot for the via, the low-priority part can land. The same applies to test points. The goal is to get away from the dense area and find a home for the test point.

Figure 7. There are times when everything else must step aside and clear all layers for a printed antenna. A net short property can tie the antenna shape and the ground via so the two can coexist at DC and at the antenna’s frequency. Like most of these slides, this one is made up entirely from scratch. The takeaway is that ground vias are always in demand around features like this one.

Like going back to the good old days, this process uses the organic, free-range kind of intelligence that comes straight from the brain. Sometimes it helps to flip the bit. Mirror the board’s image. Soften the color palette. Make the process easier. Working from home, when possible, can also help.

Either way, via stubs are one consideration during fanout. If the chip is on layer 1, the higher layer numbers are the best choice for differential pairs and similar routing. If the route is on layer 3, there will be a stub from layer 3 to the bottom. Backdrilling should be avoided when possible. Via stubs can become a signal integrity concern as the layer count increases. With that advice, the remaining studies will move on to high density interconnect (HDI) implementation.End of article content

John Burkhert, Jr. is a principle PCB designer in retirement. For the past several years, he has been sharing what he has learned for the sake of helping fresh and ambitious PCB designers. The knowledge is passed along through stories and lessons learned from three decades of design, including the most basic one-layer board up to the high-reliability rigid-flex HDI designs for aerospace and military applications. John’s well-earned free time is spent on a bike, or with a mic doing a karaoke jam.